i.MX ProcessorsのトピックRe: EIM Burst configuration

EIM Burst configuration

mauroscoccia — Tue, 16 Apr 2019 09:58:32 GMT

Hello.
I'm trying to connect an FPGA with the microprocessor (MCIMX6QSAVT10AD) via eim bus.
I would like to know how to configure the burst in both writing and reading
The various setups used by me allow me to write or read a maximum of 2 16-bit words with a single chip select transaction.
If I try to perform a write access for example of 3 16-bit words, I see on the bus a chip select transaction to write the third word, and then at a distance of 400 ns another transaction is seen relating to the first 2 words
I enclose the waveforms of the various signals involved to better explain the problem.

Re: EIM Burst configuration

igorpadykov — Wed, 17 Apr 2019 07:15:25 GMT

Hi mauro

https://community.nxp.com/docs/DOC-106467

also one can look at i.mx53 eim example and port it to i.mx6q

Sample code to use i.MX6DQ EIM burst access.

For porting may be useful baremetal sdk, it may be found on thread

SMP Enable in IMX6

Best regards
igor
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Re: EIM Burst configuration

mauroscoccia — Wed, 17 Apr 2019 09:25:59 GMT

Hi igor,

just another information.

I performed some tests and I verified that between two consecutive accesses to the bus spend about 300 nsec.

Is this a normal operation of the bus, or do I make a wrong setup?

With those latencies the bus performance is much lower than expected.

The register setup used is the follows :

GCR1 is

GCR2 is

RCR1 is

RCR2 is

WCR1 is

WCR2 is

WCR is

WIAR is

Thank you.

Re: EIM Burst configuration

igorpadykov — Wed, 17 Apr 2019 10:43:17 GMT

Hi mauro

EIM timings are described in sect.4.9.3 External Interface Module (EIM)

i.MX6DQ Datasheet

http://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf

Best regards
igor

Re: EIM Burst configuration

mauroscoccia — Wed, 17 Apr 2019 13:48:12 GMT

I saw the document you sent me, but unfortunately does not refer to the time between two consecutive accesses to the bus.

From My tests it would seem that there is this latency, but I do not know why and I can not find the way (if it exists) to decrease the latency values mentioned in the previous email.

Is it possible that these latencies are normal?

Can you help me?

Thank you.

Mauro.

Da: igorpadykov

Inviato: mercoledì 17 aprile 2019 12:44

A: Mauro Scoccia

Oggetto: Re: - Re: EIM Burst configuration

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Re: EIM Burst configuration

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Re: EIM Burst configuration

igorpadykov — Wed, 17 Apr 2019 23:32:04 GMT

time between two consecutive accesses to the eim bus is defined by

internal bus delays of processor, depends on overall processor loading.

In general you can not significantly decrease it. One can try to decrease

processor loading removing all other applications or increase master priority

using suggestions in Chapter 45 Network Interconnect Bus System (NIC-301)

i.MX6Q Reference Manual.

Best regards
igor

Re: EIM Burst configuration

igorpadykov — Thu, 18 Apr 2019 05:06:56 GMT

one can run test with baremetal sdk example, it provides minimal latency.

Best regards
igor

Re: EIM Burst configuration

Champ101 — Wed, 18 May 2022 13:07:10 GMT

Hello mauroscoccia,

Can you tell me what was the Read & Write burst length that you could get?

I use similar set-up like yours. I can read 16 words (16-bit) in a burst and write 4 words (16-bit) in a burst. Does this match with your end result?

Thanks,

Anuja