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    <title>topic iMX RT 1020 - FlexSPI NOR boot to RAM in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX-RT-1020-FlexSPI-NOR-boot-to-RAM/m-p/894192#M135147</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi All&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The following diagram shows the boot flow chart when booting from FlexSPI NOR:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/81136iE0A8D6F7BAA3598A/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;but there are two things that are not clear:&lt;/P&gt;&lt;P&gt;1. How is the Image == XIP performed and controlled? &lt;STRONG&gt;Is it an entry like the boot start location in the "boot data"?&lt;/STRONG&gt;&lt;BR /&gt;2. The flow diagram shows that the boot loader will copy the image (from FlexSPI NOR) to OCRAM when the test is false. Why does it copy to OCRAM? Is it because it is the largest SRAM block (128k)? Why not to ITCRAM (instruction tightly coupled)?&lt;BR /&gt;&lt;BR /&gt;Regards&lt;BR /&gt;&lt;BR /&gt;Mark&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 May 2019 02:37:31 GMT</pubDate>
    <dc:creator>mjbcswitzerland</dc:creator>
    <dc:date>2019-05-15T02:37:31Z</dc:date>
    <item>
      <title>iMX RT 1020 - FlexSPI NOR boot to RAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX-RT-1020-FlexSPI-NOR-boot-to-RAM/m-p/894192#M135147</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi All&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The following diagram shows the boot flow chart when booting from FlexSPI NOR:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/81136iE0A8D6F7BAA3598A/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;but there are two things that are not clear:&lt;/P&gt;&lt;P&gt;1. How is the Image == XIP performed and controlled? &lt;STRONG&gt;Is it an entry like the boot start location in the "boot data"?&lt;/STRONG&gt;&lt;BR /&gt;2. The flow diagram shows that the boot loader will copy the image (from FlexSPI NOR) to OCRAM when the test is false. Why does it copy to OCRAM? Is it because it is the largest SRAM block (128k)? Why not to ITCRAM (instruction tightly coupled)?&lt;BR /&gt;&lt;BR /&gt;Regards&lt;BR /&gt;&lt;BR /&gt;Mark&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 May 2019 02:37:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX-RT-1020-FlexSPI-NOR-boot-to-RAM/m-p/894192#M135147</guid>
      <dc:creator>mjbcswitzerland</dc:creator>
      <dc:date>2019-05-15T02:37:31Z</dc:date>
    </item>
    <item>
      <title>Re: iMX RT 1020 - FlexSPI NOR boot to RAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX-RT-1020-FlexSPI-NOR-boot-to-RAM/m-p/894193#M135148</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; The decision XIP or not is based on the used addresses (which may be found in the IVT). &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;For XIP boot, the image has to be built for FlexSPI address space and for non XIP the image &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;can be built to execute from Internal RAM. Basically any memory may be used for non-XIP&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;approach, but external memory should be init before using via the DCD.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt; Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 May 2019 05:00:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX-RT-1020-FlexSPI-NOR-boot-to-RAM/m-p/894193#M135148</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2019-05-15T05:00:23Z</dc:date>
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