PCIe IPU capable of FPGA FIFO-like Read/Write

etim — Tue, 14 May 2019 20:11:09 GMT

Hello-

IMX6Q

Regarding using the IPU as PCIe bus master: I'm interfacing with a FPGA FIFO implementation.

I'm assuming when a large buffer is DMA'd FROM the MX6 TO the FPGA FIFO the PCIe controller will fragment the buffer into packets consisting of the max amount of words the MX6 can support per TLP. The first fragment will be a write to the requested address and the next fragment will write to the initial address PLUS the previously written bytes; as-if the transfer was to a flat memory.

Question: Can the IPU/PCIe be configured to continually write to the same address without resorting to DMA buffers sized to the max words per TLP (eg. manual control of each transfer)?

Thanks!

Tim

Re: PCIe IPU capable of FPGA FIFO-like Read/Write

Yuri — Mon, 20 May 2019 07:20:23 GMT

Hello,

In general, the following considerations shows, that IPU may be used

as PCIe bus master with DMA.

https://community.nxp.com/docs/DOC-95014

But the following also should be taken into account:

a) this implementation is performing some data modification;

b) IPU has internal buffer size restrictions.

So, some IPU driver modifications are needed for customer’s applications.

Have a great day,

Yuri

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topic Re: PCIe IPU capable of FPGA FIFO-like Read/Write in i.MX Processors

PCIe IPU capable of FPGA FIFO-like Read/Write

Re: PCIe IPU capable of FPGA FIFO-like Read/Write