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    <title>i.MX ProcessorsのトピックRe: Regarding LVDS Data Mapping</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Regarding-LVDS-Data-Mapping/m-p/891665#M134826</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Pavan,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Sorry no, you&amp;nbsp; must use SPWG or JEIDA for data mapping.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 07 May 2019 15:11:28 GMT</pubDate>
    <dc:creator>Bio_TICFSL</dc:creator>
    <dc:date>2019-05-07T15:11:28Z</dc:date>
    <item>
      <title>Regarding LVDS Data Mapping</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Regarding-LVDS-Data-Mapping/m-p/891664#M134825</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Currently I am using Controller iMX6SoloX. We are designing a custom Board.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The LVDS Receiver we are using "SN64LVDS314" which is 27-Bit Serial-TO-Parallel Receiver. But SoloX Board support 28Bit Data Mapping.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can skip Bit(CTL) as mention in Reference Manual(IMX6SXRM)&amp;nbsp;Table 38-5. SPWG/PSWG/VESA 18/24 bpp Data Mapping.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Because we are using a QVGA Display.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 25 Apr 2019 09:03:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Regarding-LVDS-Data-Mapping/m-p/891664#M134825</guid>
      <dc:creator>pavan_kote</dc:creator>
      <dc:date>2019-04-25T09:03:26Z</dc:date>
    </item>
    <item>
      <title>Re: Regarding LVDS Data Mapping</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Regarding-LVDS-Data-Mapping/m-p/891665#M134826</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Pavan,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Sorry no, you&amp;nbsp; must use SPWG or JEIDA for data mapping.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 07 May 2019 15:11:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Regarding-LVDS-Data-Mapping/m-p/891665#M134826</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2019-05-07T15:11:28Z</dc:date>
    </item>
    <item>
      <title>Re: Regarding LVDS Data Mapping</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Regarding-LVDS-Data-Mapping/m-p/891666#M134827</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Jive,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your feedback.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks &amp;amp; Regards&lt;/P&gt;&lt;P&gt;Pavan&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 10 May 2019 05:40:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Regarding-LVDS-Data-Mapping/m-p/891666#M134827</guid>
      <dc:creator>pavan_kote</dc:creator>
      <dc:date>2019-05-10T05:40:46Z</dc:date>
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