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    <title>topic Re: UART jitter spec at max speed in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/UART-jitter-spec-at-max-speed/m-p/891130#M134734</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;As stated, in the following, for example, considerations, the main question really &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;is how different the transmit and receive UART clocks can be. The clock mismatch&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;error about +/-2% is acceptable. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;“Determining Clock Accuracy Requirements for UART Communications”&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;A href="https://pdfserv.maximintegrated.com/en/an/AN2141.pdf" target="test_blank"&gt;https://pdfserv.maximintegrated.com/en/an/AN2141.pdf&lt;/A&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;The voting scheme allows to improve noise immunity of data samples,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;but in general clock accuracy considerations are the same, assuming &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;data are sampled at the center of bit period. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt; Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 25 Apr 2019 07:45:26 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2019-04-25T07:45:26Z</dc:date>
    <item>
      <title>UART jitter spec at max speed</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/UART-jitter-spec-at-max-speed/m-p/891129#M134733</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;What is the tolerable jitter for imx6 UART at max speed of 4mbps?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The reference manual makes claims that there are new improvements to voting mechanism triggering that improve performance. Is this already accounted for in datasheet spec? From what I understand datasheet is claiming 6% jitter per bit with max 18% per 9bit word.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Our application requires 4mbps at up to 300m so I am trying to decide if RS485 drivers need equalization to reduce jitter or not.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 25 Apr 2019 00:48:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/UART-jitter-spec-at-max-speed/m-p/891129#M134733</guid>
      <dc:creator>jakebailey</dc:creator>
      <dc:date>2019-04-25T00:48:17Z</dc:date>
    </item>
    <item>
      <title>Re: UART jitter spec at max speed</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/UART-jitter-spec-at-max-speed/m-p/891130#M134734</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;As stated, in the following, for example, considerations, the main question really &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;is how different the transmit and receive UART clocks can be. The clock mismatch&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;error about +/-2% is acceptable. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;“Determining Clock Accuracy Requirements for UART Communications”&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;A href="https://pdfserv.maximintegrated.com/en/an/AN2141.pdf" target="test_blank"&gt;https://pdfserv.maximintegrated.com/en/an/AN2141.pdf&lt;/A&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;The voting scheme allows to improve noise immunity of data samples,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;but in general clock accuracy considerations are the same, assuming &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;data are sampled at the center of bit period. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt; Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 25 Apr 2019 07:45:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/UART-jitter-spec-at-max-speed/m-p/891130#M134734</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2019-04-25T07:45:26Z</dc:date>
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