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    <title>topic Re: iMX6 Dual Boot Failure in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Dual-Boot-Failure/m-p/890848#M134689</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; Please look at ERR007926 erratum description in the Errata (ROM: 32 kHz internal oscillator timing inaccuracy may affect&lt;BR /&gt;SD/MMC, NAND, and OneNAND boot [i.MX 6Dual/6Quad Only])&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf" title="https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf"&gt;https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Also, erratum ERR009678 (ROM: SD/EMMC/NAND prematurely times out during boot [i.MX&lt;BR /&gt;6Dual/6Quad Only]) may be interesting.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Additonally, according power up sequence requirements in the Datasheet:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; POR_B signal controls the processor POR and must be immediately asserted at&lt;BR /&gt;power-up and remain asserted until the VDD_ARM_CAP, VDD_SOC_CAP, and VDD_PU_CAP&lt;BR /&gt;supplies are stable.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf" title="https://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf"&gt;https://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; So, please check Your design regarding the mentioned above comments.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt; Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 25 Apr 2019 06:36:24 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2019-04-25T06:36:24Z</dc:date>
    <item>
      <title>iMX6 Dual Boot Failure</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Dual-Boot-Failure/m-p/890847#M134688</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We have some problems on a custom board equipped with iMX6 Dual (IMX6D7CVT08AD).&lt;/P&gt;&lt;P&gt;The boards provides 1GB NAND FLASH (MT29F8G08ABACAH4:C).&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The boards provides 1GB&amp;nbsp;DDR3 DRAM (4 x H5TC2G63GFR-PBA).&lt;/SPAN&gt;&lt;BR /&gt;We produced 300 boards.&amp;nbsp;&lt;/P&gt;&lt;P&gt;About 75% of them have no problem and they boot correctly every power on / HW reset.&lt;/P&gt;&lt;P&gt;25% of them have some problems during the boot procedure. They fail booting one time on 20/30 power on.&amp;nbsp;&lt;/P&gt;&lt;P&gt;It happen both by&amp;nbsp;switch on the power of&amp;nbsp;the board than by pushing reset button. Cause of it I think it is not a problem about voltage sequences at power on.&lt;/P&gt;&lt;P&gt;The problem is the same both from NAND Flash than SD CARD boot device. So the problem is not of the specific device.&lt;/P&gt;&lt;P&gt;We have BOOT_MODE0=0 and&amp;nbsp;&lt;SPAN&gt;BOOT_MODE1=1 (internal Boot).&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;If we set boot mode as Serial Downloader, USB OTG has been always recognized by a PC so it seems a problem of some BOOT GPIO.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;We have following GPIO configurations at booting:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;- BOOT_CFG1 [7:0]&amp;nbsp; &amp;nbsp;11000000&amp;nbsp; &amp;nbsp;(NAND FLASH)&amp;nbsp; &amp;nbsp;01000000&amp;nbsp; &amp;nbsp;(SD)&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;- BOOT_CFG2 [7:0]&amp;nbsp; &amp;nbsp;00000000&amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;- BOOT_CFG3 [7:0]&amp;nbsp; &amp;nbsp;not connected (floating)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;- BOOT_CFG4 [7:0]&amp;nbsp; &lt;SPAN&gt;not connected (floating)&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Could be a problem about floating BOOT gPIO?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;At the moment we are using an external Watchdog HW in order to solve the problem but we would understand the cause of boot failure.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 24 Apr 2019 13:03:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-Dual-Boot-Failure/m-p/890847#M134688</guid>
      <dc:creator>giacomobiancala</dc:creator>
      <dc:date>2019-04-24T13:03:27Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6 Dual Boot Failure</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Dual-Boot-Failure/m-p/890848#M134689</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; Please look at ERR007926 erratum description in the Errata (ROM: 32 kHz internal oscillator timing inaccuracy may affect&lt;BR /&gt;SD/MMC, NAND, and OneNAND boot [i.MX 6Dual/6Quad Only])&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf" title="https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf"&gt;https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Also, erratum ERR009678 (ROM: SD/EMMC/NAND prematurely times out during boot [i.MX&lt;BR /&gt;6Dual/6Quad Only]) may be interesting.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Additonally, according power up sequence requirements in the Datasheet:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; POR_B signal controls the processor POR and must be immediately asserted at&lt;BR /&gt;power-up and remain asserted until the VDD_ARM_CAP, VDD_SOC_CAP, and VDD_PU_CAP&lt;BR /&gt;supplies are stable.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf" title="https://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf"&gt;https://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; So, please check Your design regarding the mentioned above comments.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt; Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 25 Apr 2019 06:36:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-Dual-Boot-Failure/m-p/890848#M134689</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2019-04-25T06:36:24Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6 Dual Boot Failure</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Dual-Boot-Failure/m-p/890849#M134690</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank You for quick replay.&lt;/P&gt;&lt;P&gt;Today I have performed some tests.&lt;/P&gt;&lt;P&gt;I have verified when reset signal goes high both power supplies than 32KHz oscillator are stable.&lt;/P&gt;&lt;P&gt;Moreover I think the problem is not about power sequences because if I just push HW reset of processor the boot failure could happen again. In this case all the power supplies are stable.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Also ERR7926 seems not related to my&amp;nbsp;problem because when reset signal is deasserted 32Khz clock is always present.&lt;/P&gt;&lt;P&gt;Tomorrow I will check something about&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;ERR009678.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Thank You,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Giacomo&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 29 Apr 2019 16:12:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-Dual-Boot-Failure/m-p/890849#M134690</guid>
      <dc:creator>giacomobiancala</dc:creator>
      <dc:date>2019-04-29T16:12:41Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6 Dual Boot Failure</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Dual-Boot-Failure/m-p/890850#M134691</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;You may create request&amp;nbsp; \ ticket in order to review the schematic.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com/support/support:SUPPORTHOME?tid=sbmenu"&gt;https://www.nxp.com/support/support:SUPPORTHOME?tid=sbmenu&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 30 Apr 2019 05:36:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-Dual-Boot-Failure/m-p/890850#M134691</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2019-04-30T05:36:53Z</dc:date>
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