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    <title>topic Re: A9 and SDMA Core Mutual Exclusion in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/A9-and-SDMA-Core-Mutual-Exclusion/m-p/890412#M134650</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Paul&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;unfortunately nxp does not support sdma programming, that is no documentation, app notes&lt;/P&gt;&lt;P&gt;or programming guides are available. If you have special task for developing application with sdma&lt;/P&gt;&lt;P&gt;suggest to proceed with &lt;A class="link-titled" href="https://www.nxp.com/support/support/nxp-professional-services:PROFESSIONAL-SERVICE" title="https://www.nxp.com/support/support/nxp-professional-services:PROFESSIONAL-SERVICE"&gt;NXP Professional Services | NXP&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 13 May 2019 04:59:12 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2019-05-13T04:59:12Z</dc:date>
    <item>
      <title>A9 and SDMA Core Mutual Exclusion</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/A9-and-SDMA-Core-Mutual-Exclusion/m-p/890409#M134647</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am looking at section 55.7 of the document IMX6DQRM and noticed that the CCBs and BDs are located in the A9 memory space. The language in the document seems to imply that both processes in the A9 and&amp;nbsp;the ROM scripts in the SDMA core both read and write to these structures. How does the A9 and SDMA core coordinate their access to these data structures?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I do not see any software mutual exclusion implemented in the SDMA Linux drivers and I cannot determine what the ROM scripts are doing since they are not open source.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 11 May 2019 23:58:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/A9-and-SDMA-Core-Mutual-Exclusion/m-p/890409#M134647</guid>
      <dc:creator>paul_katarzis</dc:creator>
      <dc:date>2019-05-11T23:58:57Z</dc:date>
    </item>
    <item>
      <title>Re: A9 and SDMA Core Mutual Exclusion</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/A9-and-SDMA-Core-Mutual-Exclusion/m-p/890410#M134648</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Paul&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;some examples and descriptions of sdma programming can be found in&lt;/P&gt;&lt;P&gt;baremetal sdk document iMX6_Firmware_Guide.pdf Chapter 29 Configuring&lt;BR /&gt;the SDMA Driver (zip can be found on &lt;A _jive_internal="true" href="https://community.nxp.com/thread/432859)"&gt;)&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/301467"&gt;MX25 SDMA CSPI example&lt;/A&gt;&amp;nbsp;&lt;BR /&gt;&lt;A class="link-titled" href="http://billauer.co.il/blog/2011/10/imx-sdma-howto-memory-map/" title="http://billauer.co.il/blog/2011/10/imx-sdma-howto-memory-map/"&gt;Freescale i.MX SDMA tutorial (part I)&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 12 May 2019 22:55:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/A9-and-SDMA-Core-Mutual-Exclusion/m-p/890410#M134648</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-05-12T22:55:47Z</dc:date>
    </item>
    <item>
      <title>Re: A9 and SDMA Core Mutual Exclusion</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/A9-and-SDMA-Core-Mutual-Exclusion/m-p/890411#M134649</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I don't feel this addresses the question that I asked. I am interested in how the AP and SDMA core ensure only one of them has exclusive access to the CCBs and DBs. Looking at the Linux SDMA driver, it seems that no mechanism is being used to ensure that the SDMA core is not accessing the CCBs and DBs while the driver is accessing them. None of the documents provided demonstrate how the ROM scripts might be doing this.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am currently investigating an issue where the SDMA core&amp;nbsp;seems to randomly stop issuing interrupts to the AP.&amp;nbsp;The likely explanation at the moment is that there is a race condition caused by the Linux SDMA interrupt handler and ROM scripts modifying the D flag of the DBs.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 13 May 2019 03:59:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/A9-and-SDMA-Core-Mutual-Exclusion/m-p/890411#M134649</guid>
      <dc:creator>paul_katarzis</dc:creator>
      <dc:date>2019-05-13T03:59:43Z</dc:date>
    </item>
    <item>
      <title>Re: A9 and SDMA Core Mutual Exclusion</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/A9-and-SDMA-Core-Mutual-Exclusion/m-p/890412#M134650</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Paul&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;unfortunately nxp does not support sdma programming, that is no documentation, app notes&lt;/P&gt;&lt;P&gt;or programming guides are available. If you have special task for developing application with sdma&lt;/P&gt;&lt;P&gt;suggest to proceed with &lt;A class="link-titled" href="https://www.nxp.com/support/support/nxp-professional-services:PROFESSIONAL-SERVICE" title="https://www.nxp.com/support/support/nxp-professional-services:PROFESSIONAL-SERVICE"&gt;NXP Professional Services | NXP&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 13 May 2019 04:59:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/A9-and-SDMA-Core-Mutual-Exclusion/m-p/890412#M134650</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-05-13T04:59:12Z</dc:date>
    </item>
    <item>
      <title>Re: A9 and SDMA Core Mutual Exclusion</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/A9-and-SDMA-Core-Mutual-Exclusion/m-p/890413#M134651</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am not asking for help with SDMA programming. I have asked twice what mechanism is being used to prevent the A9 and SDMA core from accessing the CCBs and DBs at the same time in firmware and software distributed by Freescale/NXP.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 13 May 2019 14:14:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/A9-and-SDMA-Core-Mutual-Exclusion/m-p/890413#M134651</guid>
      <dc:creator>paul_katarzis</dc:creator>
      <dc:date>2019-05-13T14:14:13Z</dc:date>
    </item>
    <item>
      <title>Re: A9 and SDMA Core Mutual Exclusion</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/A9-and-SDMA-Core-Mutual-Exclusion/m-p/890414#M134652</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Paul&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;general approach is that A9 should prepare all sdma structures and then&lt;/P&gt;&lt;P&gt;start sdma, then it should not change CCBs and DB. One can read&amp;nbsp;Chapter 29&lt;/P&gt;&lt;P&gt;Configuring the SDMA Driver iMX6_Firmware_Guide.pdf.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 13 May 2019 14:54:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/A9-and-SDMA-Core-Mutual-Exclusion/m-p/890414#M134652</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-05-13T14:54:59Z</dc:date>
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