i.MX ProcessorsのトピックESAI I2S CONFIGURATION

ESAI I2S CONFIGURATION

abdulhussain — Mon, 25 Feb 2019 16:01:15 GMT

Hi,

I am trying to configure ESAI in normal mode with i2s data format for the configuration tx1 pin connected to external dsp. For this I have written dummy codec driver. But it is transmitting data only in tx0 pin. May i know how to drive data in tx1 pin instead of tx0.

Regards,

Abdul

Re: ESAI I2S CONFIGURATION

igorpadykov — Tue, 26 Feb 2019 02:13:46 GMT

Hi Abdul

one can try to change TEx bits in Transmit FIFO Configuration Register (TFCR),

simple example with ESAI configuration can be found in i.MX6 SDK (1.1.0_iMX6_Platform_SDK.zip) on

SMP Enable in IMX6

Best regards
igor
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Re: ESAI I2S CONFIGURATION

abdulhussain — Tue, 26 Feb 2019 05:34:50 GMT

Hi Igor,

We are using imx8dx chipset. As you mentioned, sdk has bare metal programming example. We trying to achieve this configuration from Linux.

As per my understanding, fsl_esai_hw_params function in fsl_esai.c configures transmitter fifo enable bits based on the channels and slots,

u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);

val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
(tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));

Also in fsl_esai_trigger function, transmitter enable bits configured in TCR register which is also based on channels and slots.

So for example if i select channels as 2 and slots as 2 for normal mode, it gives pins value as 1 and select TX0 pins.

Can you guide us to drive data in normal mode from TX1 pin?

Regards,

Abdul

Re: ESAI I2S CONFIGURATION

igorpadykov — Tue, 26 Feb 2019 05:44:16 GMT

Hi Abdul

I am afraid this is not configurable, so one will have to make

modifications in esai driver. Since these changes are not obvious and

straightforward due to complexity of alsa drivers, suggest to proceed with

extended support of NXP Professional Services | NXP

Best regards
igor

Re: ESAI I2S CONFIGURATION

abdulhussain — Tue, 26 Feb 2019 06:06:13 GMT

Thanks for the reply Igor.