<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
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    <title>topic Re: wrong FCB structure written on NAND in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/wrong-FCB-structure-written-on-NAND/m-p/886955#M134324</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;it seems that the "missing" data began at offset 0xC5, and the values there are correct. What it's not clear is why there's this (BCH?) data so soon; we expected the Block0 size to be 512 bytes for i.MX6ULL.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 12 Mar 2019 10:45:52 GMT</pubDate>
    <dc:creator>da1</dc:creator>
    <dc:date>2019-03-12T10:45:52Z</dc:date>
    <item>
      <title>wrong FCB structure written on NAND</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/wrong-FCB-structure-written-on-NAND/m-p/886954#M134323</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;it seems that we have a problem with the &lt;STRONG&gt;FCB data structure written on NAND&lt;/STRONG&gt;, on boards based on i.MX6ULL rev1.0 14x14 EVK, booting from a &lt;STRONG&gt;Micron MT29F32G08CBADAWP-12IT:D&lt;/STRONG&gt; NAND.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;From some point on, the data seems to be wrong; can anyone with experience on the subject confirm our analysis?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We tried using multiple versions of kobs-ng, including the latest from github and the one in the SDK from NXP.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What we see in the NAND, with a &lt;EM&gt;nanddump -o -a /dev/mtd0&lt;/EM&gt; is as follow (we've removed the first 0x15 bytes to be aligned with the FCB structure described in chapter 8.5.2.3 of the &lt;STRONG&gt;i.MX 6ULL Applications Processor Reference Manual&lt;/STRONG&gt;:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="nand.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/72972iAB7129C9DD3286A7/image-size/large?v=v2&amp;amp;px=999" role="button" title="nand.png" alt="nand.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Everything is ok up to &lt;STRONG&gt;BadBlockMarkerByte&lt;/STRONG&gt; (position 0x7c, value 7692); after that, there should be &lt;STRONG&gt;0&lt;/STRONG&gt; for &lt;STRONG&gt;BadBlockMarkerStartBit&lt;/STRONG&gt; but as you can see everthing from there on seems to be wrong.&lt;/P&gt;&lt;P&gt;We are especially concerned about &lt;STRONG&gt;BCHType&lt;/STRONG&gt; that should be 1, but is wrong and we suspect it makes ECC flipbits recovery impossible, for the ROM.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The structure, as printed by kobs-ng:&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;# kobs-ng init -x -v --chip_0_device_path=/dev/mtd0 u-boot.imx&lt;BR /&gt;MTD CONFIG:&lt;BR /&gt;&amp;nbsp; chip_0_device_path = "/dev/mtd0"&lt;BR /&gt;&amp;nbsp; chip_1_device_path = "(null)"&lt;BR /&gt;&amp;nbsp; search_exponent = 2&lt;BR /&gt;&amp;nbsp; data_setup_time = 80&lt;BR /&gt;&amp;nbsp; data_hold_time = 60&lt;BR /&gt;&amp;nbsp; address_setup_time = 25&lt;BR /&gt;&amp;nbsp; data_sample_time = 6&lt;BR /&gt;&amp;nbsp; row_address_size = 3&lt;BR /&gt;&amp;nbsp; column_address_size = 2&lt;BR /&gt;&amp;nbsp; read_command_code1 = 0&lt;BR /&gt;&amp;nbsp; read_command_code2 = 48&lt;BR /&gt;&amp;nbsp; boot_stream_major_version = 1&lt;BR /&gt;&amp;nbsp; boot_stream_minor_version = 0&lt;BR /&gt;&amp;nbsp; boot_stream_sub_version = 0&lt;BR /&gt;&amp;nbsp; ncb_version = 3&lt;BR /&gt;&amp;nbsp; boot_stream_1_address = 0&lt;BR /&gt;&amp;nbsp; boot_stream_2_address = 0&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp; -- We add the 1k-padding to the uboot.&lt;BR /&gt;.tmp_kobs_ng: verifying using key '00000000000000000000000000000000'&lt;BR /&gt;.tmp_kobs_ng: is a valid bootstream for key '00000000000000000000000000000000'&lt;BR /&gt;mtd: use new bch layout raw access mode&lt;BR /&gt;mtd: opening: "/dev/mtd0"&lt;BR /&gt;NFC geometry :&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;ECC Strength&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; : 40&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;Page Size in Bytes : 8762&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;Metadata size&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; : 10&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;ECC Chunk Size in byte : 1024&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;ECC Chunk count&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; : 8&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;Block Mark Byte Offset : 7692&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;Block Mark Bit Offset&amp;nbsp; : 0&lt;BR /&gt;====================================================&lt;BR /&gt;mtd: opened '/dev/mtd0' - '(null)'&lt;BR /&gt;mtd: max_boot_stream_size_in_bytes = 25165824&lt;BR /&gt;mtd: boot_stream_size_in_bytes = 475136&lt;BR /&gt;mtd: boot_stream_size_in_pages = 58&lt;BR /&gt;mtd: #1 0x01000000 - 0x02800000 (0x01074000)&lt;BR /&gt;mtd: #2 0x02800000 - 0x04000000 (0x02874000)&lt;BR /&gt;FCB&lt;BR /&gt;&amp;nbsp; m_u32Checksum = 0x00000000&lt;BR /&gt;&amp;nbsp; m_u32FingerPrint = 0x20424346&lt;BR /&gt;&amp;nbsp; m_u32Version = 0x01000000&lt;BR /&gt;&amp;nbsp; m_NANDTiming.m_u8DataSetup = 80&lt;BR /&gt;&amp;nbsp; m_NANDTiming.m_u8DataHold = 60&lt;BR /&gt;&amp;nbsp; m_NANDTiming.m_u8AddressSetup = 25&lt;BR /&gt;&amp;nbsp; m_NANDTiming.m_u8DSAMPLE_TIME = 6&lt;BR /&gt;&amp;nbsp; m_u32PageDataSize = 8192&lt;BR /&gt;&amp;nbsp; m_u32TotalPageSize = 8936&lt;BR /&gt;&amp;nbsp; m_u32SectorsPerBlock = 256&lt;BR /&gt;&amp;nbsp; m_u32NumberOfNANDs = 0&lt;BR /&gt;&amp;nbsp; m_u32TotalInternalDie = 0&lt;BR /&gt;&amp;nbsp; m_u32CellType = 0&lt;BR /&gt;&amp;nbsp; m_u32EccBlockNEccType = 20&lt;BR /&gt;&amp;nbsp; m_u32EccBlock0Size = 1024&lt;BR /&gt;&amp;nbsp; m_u32EccBlockNSize = 1024&lt;BR /&gt;&amp;nbsp; m_u32EccBlock0EccType = 20&lt;BR /&gt;&amp;nbsp; m_u32MetadataBytes = 10&lt;BR /&gt;&amp;nbsp; m_u32NumEccBlocksPerPage = 7&lt;BR /&gt;&amp;nbsp; m_u32EccBlockNEccLevelSDK = 0&lt;BR /&gt;&amp;nbsp; m_u32EccBlock0SizeSDK = 0&lt;BR /&gt;&amp;nbsp; m_u32EccBlockNSizeSDK = 0&lt;BR /&gt;&amp;nbsp; m_u32EccBlock0EccLevelSDK = 0&lt;BR /&gt;&amp;nbsp; m_u32NumEccBlocksPerPageSDK = 0&lt;BR /&gt;&amp;nbsp; m_u32MetadataBytesSDK = 0&lt;BR /&gt;&amp;nbsp; m_u32EraseThreshold = 0&lt;BR /&gt;&amp;nbsp; m_u32Firmware1_startingPage = 2048&lt;BR /&gt;&amp;nbsp; m_u32Firmware2_startingPage = 5120&lt;BR /&gt;&amp;nbsp; m_u32PagesInFirmware1 = 58&lt;BR /&gt;&amp;nbsp; m_u32PagesInFirmware2 = 58&lt;BR /&gt;&amp;nbsp; m_u32DBBTSearchAreaStartAddress = 1024&lt;BR /&gt;&amp;nbsp; m_u32BadBlockMarkerByte = 7692&lt;BR /&gt;&amp;nbsp; m_u32BadBlockMarkerStartBit = 0&lt;BR /&gt;&amp;nbsp; m_u32BBMarkerPhysicalOffset = 8192&lt;BR /&gt;&amp;nbsp; m_u32BCHType = 1&lt;BR /&gt;&amp;nbsp; m_NANDTMTiming.m_u32TMTiming2_ReadLatency = 0&lt;BR /&gt;&amp;nbsp; m_NANDTMTiming.m_u32TMTiming2_PreambleDelay = 0&lt;BR /&gt;&amp;nbsp; m_NANDTMTiming.m_u32TMTiming2_CEDelay = 0&lt;BR /&gt;&amp;nbsp; m_NANDTMTiming.m_u32TMTiming2_PostambleDelay = 0&lt;BR /&gt;&amp;nbsp; m_NANDTMTiming.m_u32TMTiming2_CmdAddPause = 0&lt;BR /&gt;&amp;nbsp; m_NANDTMTiming.m_u32TMTiming2_DataPause = 0&lt;BR /&gt;&amp;nbsp; m_NANDTMTiming.m_u32TMSpeed = 0&lt;BR /&gt;&amp;nbsp; m_NANDTMTiming.m_u32TMTiming1_BusyTimeout = 0&lt;BR /&gt;&amp;nbsp; m_u32DISBBM = 0&lt;BR /&gt;&amp;nbsp; m_u32BBMarkerPhysicalOffsetInSpareData = 0&lt;BR /&gt;&amp;nbsp; m_u32OnfiSyncEnable = 0&lt;BR /&gt;&amp;nbsp; m_NANDONFITiming.m_u32ONFISpeed = 0&lt;BR /&gt;&amp;nbsp; m_NANDONFITiming.m_u32ONFITiming_ReadLatency = 0&lt;BR /&gt;&amp;nbsp; m_NANDONFITiming.m_u32ONFITiming_CEDelay = 0&lt;BR /&gt;&amp;nbsp; m_NANDONFITiming.m_u32ONFITiming_PreambleDelay = 0&lt;BR /&gt;&amp;nbsp; m_NANDONFITiming.m_u32ONFITiming_PostambleDelay = 0&lt;BR /&gt;&amp;nbsp; m_NANDONFITiming.m_u32ONFITiming_CmdAddPause = 0&lt;BR /&gt;&amp;nbsp; m_NANDONFITiming.m_u32ONFITiming_DataPause = 0&lt;BR /&gt;&amp;nbsp; m_NANDONFITiming.m_u32ONFITiming_BusyTimeout = 0&lt;BR /&gt;&amp;nbsp; m_u32DISBBSearch = 0&lt;BR /&gt;&amp;nbsp; m_u32RandomizerEnable = 0&lt;BR /&gt;&amp;nbsp; m_u32ReadRetryEnable = 0&lt;BR /&gt;&amp;nbsp; m_u32ReadRetrySeqLength = 0&lt;BR /&gt;DBBT&lt;BR /&gt;&amp;nbsp; m_u32Checksum = 0x00000000&lt;BR /&gt;&amp;nbsp; m_u32FingerPrint = 0x54424244&lt;BR /&gt;&amp;nbsp; m_u32Version = 0x01000000&lt;BR /&gt;&amp;nbsp; m_u32DBBTNumOfPages = 0&lt;BR /&gt;Firmware: image #0 @ 0x1000000 size 0x74000 - available 0x1800000&lt;BR /&gt;Firmware: image #1 @ 0x2800000 size 0x74000 - available 0x1800000&lt;BR /&gt;-------------- Start to write the [ FCB ] -----&lt;BR /&gt;mtd: erasing @0:0x0-0x200000&lt;BR /&gt;mtd: Writing FCB0 [ @0:0x0 ] (22e8) *&lt;BR /&gt;mtd: erasing @0:0x200000-0x400000&lt;BR /&gt;mtd: Writing FCB1 [ @0:0x200000 ] (22e8) *&lt;BR /&gt;mtd: erasing @0:0x400000-0x600000&lt;BR /&gt;mtd: Writing FCB2 [ @0:0x400000 ] (22e8) *&lt;BR /&gt;mtd: erasing @0:0x600000-0x800000&lt;BR /&gt;mtd: Writing FCB3 [ @0:0x600000 ] (22e8) *&lt;BR /&gt;mtd_commit_bcb(FCB): status 0&lt;BR /&gt;&lt;BR /&gt;-------------- Start to write the [ DBBT ] -----&lt;BR /&gt;mtd: erasing @0:0x800000-0xa00000&lt;BR /&gt;mtd: Writing DBBT0 [ @0:0x800000 ] (2000) *&lt;BR /&gt;mtd: erasing @0:0xa00000-0xc00000&lt;BR /&gt;mtd: Writing DBBT1 [ @0:0xa00000 ] (2000) *&lt;BR /&gt;mtd: erasing @0:0xc00000-0xe00000&lt;BR /&gt;mtd: Writing DBBT2 [ @0:0xc00000 ] (2000) *&lt;BR /&gt;mtd: erasing @0:0xe00000-0x1000000&lt;BR /&gt;mtd: Writing DBBT3 [ @0:0xe00000 ] (2000) *&lt;BR /&gt;mtd_commit_bcb(DBBT): status 0&lt;BR /&gt;&lt;BR /&gt;---------- Start to write the [ .tmp_kobs_ng ]----&lt;BR /&gt;mtd: Writting .tmp_kobs_ng: #0 @0: 0x01000000 - 0x01074000&lt;BR /&gt;mtd: erasing @0:0x1000000-0x1200000&lt;BR /&gt;mtd: We write one page for save guard. *&lt;BR /&gt;mtd: Writting .tmp_kobs_ng: #1 @0: 0x02800000 - 0x02874000&lt;BR /&gt;mtd: erasing @0:0x2800000-0x2a00000&lt;BR /&gt;mtd: We write one page for save guard. *&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;kobs-ng correctly identifies the processor as i.MX6ULL.&amp;nbsp; Our kernel is the latest from &lt;STRONG&gt;imx_4.1.15_2.0.0_ga&lt;/STRONG&gt; branch from NXP.&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;# cat /proc/cpuinfo&lt;BR /&gt;processor&amp;nbsp;&amp;nbsp; &amp;nbsp;: 0&lt;BR /&gt;model name&amp;nbsp;&amp;nbsp; &amp;nbsp;: ARMv7 Processor rev 5 (v7l)&lt;BR /&gt;BogoMIPS&amp;nbsp;&amp;nbsp; &amp;nbsp;: 3.00&lt;BR /&gt;Features&amp;nbsp;&amp;nbsp; &amp;nbsp;: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae&lt;BR /&gt;CPU implementer&amp;nbsp;&amp;nbsp; &amp;nbsp;: 0x41&lt;BR /&gt;CPU architecture: 7&lt;BR /&gt;CPU variant&amp;nbsp;&amp;nbsp; &amp;nbsp;: 0x0&lt;BR /&gt;CPU part&amp;nbsp;&amp;nbsp; &amp;nbsp;: 0xc07&lt;BR /&gt;CPU revision&amp;nbsp;&amp;nbsp; &amp;nbsp;: 5&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hardware&amp;nbsp;&amp;nbsp; &amp;nbsp;: Freescale i.MX6 Ultralite (Device Tree)&lt;BR /&gt;Revision&amp;nbsp;&amp;nbsp; &amp;nbsp;: 0000&lt;BR /&gt;Serial&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;: 0000000000000000&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This problem was detected investigating &lt;A href="https://community.nxp.com/thread/497005"&gt;i.MX6ULL errors correcting u-boot bitflips&lt;/A&gt; (still unresolved).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We also tried switching the a 2017.03 u-boot-imx (from the previous 2016.03), but nothing changed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you in advance for any help.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 12 Mar 2019 07:54:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/wrong-FCB-structure-written-on-NAND/m-p/886954#M134323</guid>
      <dc:creator>da1</dc:creator>
      <dc:date>2019-03-12T07:54:54Z</dc:date>
    </item>
    <item>
      <title>Re: wrong FCB structure written on NAND</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/wrong-FCB-structure-written-on-NAND/m-p/886955#M134324</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;it seems that the "missing" data began at offset 0xC5, and the values there are correct. What it's not clear is why there's this (BCH?) data so soon; we expected the Block0 size to be 512 bytes for i.MX6ULL.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 12 Mar 2019 10:45:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/wrong-FCB-structure-written-on-NAND/m-p/886955#M134324</guid>
      <dc:creator>da1</dc:creator>
      <dc:date>2019-03-12T10:45:52Z</dc:date>
    </item>
    <item>
      <title>Re: wrong FCB structure written on NAND</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/wrong-FCB-structure-written-on-NAND/m-p/886956#M134325</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;This may help you.&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" class="link-titled" href="https://community.nxp.com/message/947634?commentID=947634#comment-947634" title="https://community.nxp.com/message/947634?commentID=947634#comment-947634"&gt;https://community.nxp.com/message/947634?commentID=947634#comment-947634&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 27 Mar 2019 06:26:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/wrong-FCB-structure-written-on-NAND/m-p/886956#M134325</guid>
      <dc:creator>jimmychan</dc:creator>
      <dc:date>2019-03-27T06:26:32Z</dc:date>
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