i.MX ProcessorsのトピックRe: i.MX25 NAND, Boot Question

i.MX25 NAND, Boot Question

jwsawyer — Fri, 22 Feb 2019 18:00:16 GMT

We would like to use a Micron MT29F1G08ABAEAWP NAND Flash memory device.with the i.MX25.

The Micron NAND x8 device is organized using a 2048 page size plus 64 spare bytes.

We are using these settings:

BT_PAGE_SIZE = 01 (2K)

BT_BUS_WIDTH = 00 (8b)

BT_MLS_SEL = 0 (SLC)

BT_SPARE_SIZE = 0

BT_MEM_CTRL = 01 (NAND)

BT_MEM_TYPE = 10 (5 address cycles)

We think this memory should work with the i.MX25. It does have this cryptic note in the datasheet:

Minimum required ECC for block 0 if PROGRAM/ERASE cycles are less than 1000 : 1-bit ECC per 528 bytes

Would you agree that this device should be compatible with the i.MX25 boot sequence and NFC operations?

If yes, we don't see the i.MX25 boot sequence send the 0x30 command for the READ PAGE command, so the NAND does not output data.

Thank you!

Re: i.MX25 NAND, Boot Question

jwsawyer — Fri, 22 Feb 2019 19:28:13 GMT

Update - hardware folks found an issue with the Boot-Related pins. Once corrected, we see the expected READ PAGE operation succeed on boot.

BUT...we are still having problems with reading data out of the device using NFC commands. The read halts after 512 (maybe 528?) bytes, as REn stops being toggled by the micro. But CEn remains low, so the INT pin never indicates that the read is complete.

RCSR = 0x64000900 [NFC_FMS = 1, NFC_4K = 0, MEM_CTRL = 1, MEM_TYPE = 2, PAGE_SIZE = 1, BUS_WIDTH = 0]

NAND_FLASH_CONFIG1 = 0x0A0B

Any suggestions?

Thanks again.

Re: i.MX25 NAND, Boot Question

igorpadykov — Fri, 22 Feb 2019 23:33:24 GMT

Hi John

this part has 4-bit ECC and can be supported by i.MX25 as described

in sect.2.5 MLC/SLC NAND Devices AN3684 i.MX25 Boot Options

https://www.nxp.com/docs/en/application-note/AN3684.pdf

For programming nand boot image recommended to use ATK Tool

(it correctly handles nand bad block management) as shown in attached documents

i.MX25 PDK Board Flashing SPI NOR

Best regards
igor
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