topic Re: iMX8QM 1200MHz DDR Boot issue in i.MX Processors

iMX8QM 1200MHz DDR Boot issue

prashanthkumar — Tue, 05 Feb 2019 06:30:43 GMT

Hi,

We are working on iMX8 Quad Max custom board with 4.14.78 Kernel.

Its able to boot from DDR frequency 1600MHz. with following SCFW command.

How to boot SCFW & u-boot using 1200MHz DDR frequency in kernel?

Can you please provide commands to compile SCFW & Uboot source code.

Regards,

Prashanth Kumar K

Re: iMX8QM 1200MHz DDR Boot issue

igorpadykov — Tue, 05 Feb 2019 23:08:37 GMT

Hi Prashanth

one can check SCFW Porting Kit documentation and 1200MHz example in
scfw_export_mx8qm_b0..mx8dm_val/dcd/imx8dmddr4_dcd_1.2GHz.cfg
SCFW Porting Kit

uboot sources
uboot-imx - i.MX U-Boot

Note, for custom board cfg file should be generated using MX8QM LPDDR4 register programming

aid and ddr test tool for that part.

Best regards
igor
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Re: iMX8QM 1200MHz DDR Boot issue

prashanthkumar — Fri, 08 Feb 2019 07:32:37 GMT

Hi Igor,

We follow the above mentioned procedure for SCFW compilation.

The compilation command which is we are using as follows.

~# make qm R=B0 B=val M=1 DDR_CON=imx8qmddr4_dcd_1.2GHz
Generating platform/board/mx8qm_val/dcd/imx8qmddr4_dcd_1.2GHz.h
Generating platform/board/mx8qm_val/dcd/dcd.h from platform/board/mx8qm_val/dcd/imx8qmddr4_dcd_1.2GHz.h
Generating platform/board/mx8qm_val/dcd/imx8qmddr4_dcd_1.2GHz_retention.h
Generating platform/board/mx8qm_val/dcd/dcd_retention.h from platform/board/mx8qm_val/dcd/imx8qmddr4_dcd_1.2GHz_retention.h
Compiling platform/drivers/pmic/fsl_pmic.c
Compiling platform/drivers/pmic/pf100/fsl_pf100.c
Compiling platform/drivers/pmic/pf8100/fsl_pf8100.c
Compiling platform/board/mx8qm_val/board.c
Compiling platform/board/board_common.c
Compiling platform/board/pmic.c
Linking build_mx8qm_b0/scfw_tcm.elf ....
Objcopy build_mx8qm_b0/scfw_tcm.bin ....
done.

But while booting iMX8QM board, still its showing as "DDR frequency = 1596000000" instead of "DDR frequency = 1200000000" in SCFW terminal.

The SCFW log is given below for your reference.

DDR frequency = 1596000000
ROM boot time = 113086 usec
SCFW boot time = 31611 usec
        Banner = 13 usec
        Init    = 976 usec
        Config = 4041 usec
        DDR     = 1319 usec
        SConfig = 231 usec
        Prep    = 22891 usec

Please confirm that SCFW is hard coding the DDR frequency?

Regards,

Prashanth Kumar K

Re: iMX8QM 1200MHz DDR Boot issue

igorpadykov — Sat, 09 Feb 2019 03:50:16 GMT

Hi Prashanth

for DRC( DDR controller/phy) one can find in imx8qmddr4_dcd_1.2GHz.cfg :
    uint32_t rate2 = SC_600MHZ;
    pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2);
    pm_set_clock_rate(SC_PT, SC_R_DRC_1, SC_PM_CLK_MISC0, &rate2);

So, were you able to use MX8QM LPDDR4 register programming aid tool

and run ddr test (suggest to obtain it through local nxp office as

this part is not officially released yet).

Best regards
igor

Re: iMX8QM 1200MHz DDR Boot issue

prashanthkumar — Mon, 11 Feb 2019 04:28:33 GMT

Dear Igor,

Attached LPDDR4 stress test log file done with 1200MHz DDR frequency

along with the mail.

Best regards,

Prashanth Kumar K

Re: iMX8QM 1200MHz DDR Boot issue

igorpadykov — Mon, 11 Feb 2019 07:16:11 GMT

Hi Prashanth

may be useful to check presentation:

https://community.nxp.com/docs/DOC-341872

iMX8 Quad Max part is not officially released yet, for custom

design issues suggested to proceed with

NXP Professional Services | NXP

Best regards
igor