i.MX ProcessorsのトピックRe: Layout Design Guide Line for LPDDR4 on i.MX8QX

Layout Design Guide Line for LPDDR4 on i.MX8QX

tanno_yoshihiro — Mon, 04 Feb 2019 09:36:59 GMT

Hello,

Now, we are designing our evaluation board circuit using iMX8QX.
So we want to know the following specification for LPDDR4 Layout Design Guide Line.

1.Line Length Difference (Differential Pair P/N, CK/DQS)
2.Line Length Difference (Single - ended, CS/CKE/DMI/CA/DQ)
3.Space between Differential Pair and Other Traces
   - CK_t/c to CAx, CS_n
   - CK_t/c to CKEx
   - CK_t/c to DQSx_t/c
   - DQS_t/c to DQ
   - DMI to DQ
4.Characteristic Impedance (Z0)
5.Differential Impedance (Z0_diff)

Thanks a lot
Yoshihiro

Re: Layout Design Guide Line for LPDDR4 on i.MX8QX

Yuri — Tue, 05 Feb 2019 10:44:01 GMT

Hello,

I've sent You reply directly.

Have a great day,

Yuri

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Re: Layout Design Guide Line for LPDDR4 on i.MX8QX

sergeyserg — Mon, 29 Jul 2019 15:48:08 GMT

Hello Yuri,

Now I am doing pcb design with iMX8MMini and I have got the same questions about layout LPDDR4 only for iMX8MMini. Could you send me these layout applications LPDDR4 for iMX8MMini?

Thanks

Serg.

Re: Layout Design Guide Line for LPDDR4 on i.MX8QX

tiagoborth — Mon, 14 Sep 2020 10:44:05 GMT

Hi Yuri, it would be possible share the same information regarding iMX8QX + LPDDR4 line impedances?

Re: Layout Design Guide Line for LPDDR4 on i.MX8QX

Yuri — Tue, 15 Sep 2020 05:51:51 GMT

@tiagoborth

https://community.nxp.com/t5/Nominate-to-Knowledge-Base/LPDDR4-line-impedance-on-i-MX8QX/ta-p/1153226

Re: Layout Design Guide Line for LPDDR4 on i.MX8QX

Okiann — Thu, 03 Mar 2022 08:13:59 GMT

Hi Yuri,

May I have a copy of the guide doc in pdf? Could you send me through email if it is available to send. Thank you.

Re: Layout Design Guide Line for LPDDR4 on i.MX8QX

hrudaynath — Wed, 01 Feb 2023 19:14:12 GMT

Hi Yuri

can you please send this document to me please

hrudaynath.chaudhari@cummins.com