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    <title>topic PCIe: Virtual channels in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-Virtual-channels/m-p/881963#M133720</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hey all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I need to know which NXP MCUs/MPUs supports &lt;STRONG&gt;more then one&lt;/STRONG&gt; Virtual Channel (VC) for PCIe.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I need to realize isochronous data transfers over PCIe.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 05 Apr 2019 13:30:27 GMT</pubDate>
    <dc:creator>julian_dietrich</dc:creator>
    <dc:date>2019-04-05T13:30:27Z</dc:date>
    <item>
      <title>PCIe: Virtual channels</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-Virtual-channels/m-p/881963#M133720</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hey all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I need to know which NXP MCUs/MPUs supports &lt;STRONG&gt;more then one&lt;/STRONG&gt; Virtual Channel (VC) for PCIe.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I need to realize isochronous data transfers over PCIe.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 05 Apr 2019 13:30:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-Virtual-channels/m-p/881963#M133720</guid>
      <dc:creator>julian_dietrich</dc:creator>
      <dc:date>2019-04-05T13:30:27Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe: Virtual channels</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-Virtual-channels/m-p/881964#M133721</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Julian&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;virtual channels are supported, for example this is described in&lt;/P&gt;&lt;P&gt;sect.48.2.4 Configuration-Dependent Module (CDM)&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com/webapp/Download?colCode=IMX6DQRM" target="_blank"&gt;&lt;STRONG&gt;i.MX 6Dual/6Quad Applications Processor Reference Manual &lt;/STRONG&gt;&lt;/A&gt;&lt;/P&gt;&lt;P&gt;or sect.19.2.1.2 Features&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf" target="_blank"&gt;&lt;STRONG&gt;i.MX 8DualXPlus/8QuadXPlus Applications Processor Reference Manual &lt;/STRONG&gt;&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 06 Apr 2019 02:47:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-Virtual-channels/m-p/881964#M133721</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-04-06T02:47:39Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe: Virtual channels</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-Virtual-channels/m-p/881965#M133722</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Igor!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Maybe I'm blind but in both documents I can't find any answer about &lt;STRONG&gt;how many VC's&lt;/STRONG&gt; are supported?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Furthermore I'm quite new in the PCIe-technology and I have a general question:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I want to connect several PCIe-endpoints via a PCIe-switch and the communication between the endpoints must be isochronous.&lt;/P&gt;&lt;P&gt;Is it true, that for isochronous data transfers I need more then one VC also in the endpoints?&lt;/P&gt;&lt;P&gt;Or are the several VCs only for the PCIe switch required?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 08 Apr 2019 08:33:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-Virtual-channels/m-p/881965#M133722</guid>
      <dc:creator>julian_dietrich</dc:creator>
      <dc:date>2019-04-08T08:33:29Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe: Virtual channels</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-Virtual-channels/m-p/881966#M133723</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/julian.dietrich@hbm.com"&gt;julian.dietrich@hbm.com&lt;/A&gt; Did you solve this? curious which pcie switch you used?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 14 Aug 2019 09:54:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-Virtual-channels/m-p/881966#M133723</guid>
      <dc:creator>dav1</dc:creator>
      <dc:date>2019-08-14T09:54:44Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe: Virtual channels</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-Virtual-channels/m-p/881967#M133724</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi dav1,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It turns out that you need the VC-capability for all connected PCIe-parts in the system. So while the enumeration phase, the RC will scan the capabilities of each part/port, and when the Endpoint has only one VC, the hole communication path between RC/Switch/EP will only use one VC, even if the switch itself has more than one VC.&lt;/P&gt;&lt;P&gt;For me it doesn't make sense - but that's the way it works...&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the end we kicked all VC/TC-schemes for our system. It is very less supported by manufactures, especially for EPs.&lt;/P&gt;&lt;P&gt;We're going the way to only have realtime/isochronous data in our system. Thus, we won't have to seperate these data streams via VC/TC anymore.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 15 Aug 2019 08:30:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-Virtual-channels/m-p/881967#M133724</guid>
      <dc:creator>julian_dietrich</dc:creator>
      <dc:date>2019-08-15T08:30:18Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe: Virtual channels</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-Virtual-channels/m-p/881968#M133725</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks for the comments Julian,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;what switch IC did you use?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 21 Nov 2019 01:29:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-Virtual-channels/m-p/881968#M133725</guid>
      <dc:creator>dav1</dc:creator>
      <dc:date>2019-11-21T01:29:37Z</dc:date>
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