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    <title>i.MX Processors中的主题 Re: iMX7 CM4 LMEM DDR Caching</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX7-CM4-LMEM-DDR-Caching/m-p/878098#M133212</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; We have checked at on IMX7D(Rev 1.3) and doesn't find issue with the address 0x8020_0000 &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;for code section with cache enabled/disabled. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; Meanwhile, we do have the suggestion as per the below,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;One can change the m_data to "0x9ff00000" in the platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_ocram.ld, &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;then follow the steps to load binary into the OCRAM from Getting started doc of FreeRTOS bundle. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;If code size(text) is too higher that it cannot fit into the OCRAM then one can change DDR linker script from file platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_ddr.ld as per below, &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;m_interrupts ORIGIN = 0x9ff00000, LENGTH = 0x9ff00000 &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;m_text ORIGIN = 0x9ff00240, LENGTH = &amp;lt;As per need&amp;gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;m_data ORIGIN = 0x9ff08000, LENGTH = &amp;lt;As per need&amp;gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Then just follow the steps to load the binary at address "0x9ff00000" into external RAM. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Hope the above information will be helpful.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Have a great day,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Yuri&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Note: If this post answers your question, please click the Correct Answer &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;button. Thank you!&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 21 Feb 2019 03:16:39 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2019-02-21T03:16:39Z</dc:date>
    <item>
      <title>iMX7 CM4 LMEM DDR Caching</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7-CM4-LMEM-DDR-Caching/m-p/878097#M133211</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Yuri,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;I understand that it is highly recommended to use 0x00000000 - 0x1FFFFFFF for code. Unfortunately to have reasonable performance using DDR memory all data (code and data) must come from the system bus as has been experimentally found here:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;&lt;A href="https://blog.printk.io/2017/05/i-mx-7-cortex-m4-memory-locations-and-performance/"&gt;https://blog.printk.io/2017/05/i-mx-7-cortex-m4-memory-locations-and-performance/&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;My application requires reasonable execution performance (no more than ~2x slower than executing from TCM) and reasonable code space (more than TCM+OCRAM). Therefore I have to use the system bus and run code out of DDR.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;When I configured the MPU to have 0x8000_0000 - 0x801f_ffff as catchable and all following memory (0x8020_0000 -&amp;gt; )as uncatchable AND disable instruction access (bit 28 of MPU_RASR register) the M4 core faults with a IACCVIOL. So clearly the cache controller is messing with memory outside of the documented cacheable region. This is unexpected behavior.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;What I am looking for with this request is documentation that I can follow and not experience unexpected behavior. What can I do to help facilitate that?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Allen&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 30 Nov 2018 08:06:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7-CM4-LMEM-DDR-Caching/m-p/878097#M133211</guid>
      <dc:creator>dogisfat</dc:creator>
      <dc:date>2018-11-30T08:06:24Z</dc:date>
    </item>
    <item>
      <title>Re: iMX7 CM4 LMEM DDR Caching</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7-CM4-LMEM-DDR-Caching/m-p/878098#M133212</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; We have checked at on IMX7D(Rev 1.3) and doesn't find issue with the address 0x8020_0000 &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;for code section with cache enabled/disabled. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; Meanwhile, we do have the suggestion as per the below,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;One can change the m_data to "0x9ff00000" in the platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_ocram.ld, &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;then follow the steps to load binary into the OCRAM from Getting started doc of FreeRTOS bundle. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;If code size(text) is too higher that it cannot fit into the OCRAM then one can change DDR linker script from file platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_ddr.ld as per below, &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;m_interrupts ORIGIN = 0x9ff00000, LENGTH = 0x9ff00000 &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;m_text ORIGIN = 0x9ff00240, LENGTH = &amp;lt;As per need&amp;gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;m_data ORIGIN = 0x9ff08000, LENGTH = &amp;lt;As per need&amp;gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Then just follow the steps to load the binary at address "0x9ff00000" into external RAM. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Hope the above information will be helpful.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Have a great day,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Yuri&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Note: If this post answers your question, please click the Correct Answer &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;button. Thank you!&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 21 Feb 2019 03:16:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7-CM4-LMEM-DDR-Caching/m-p/878098#M133212</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2019-02-21T03:16:39Z</dc:date>
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