i.MX Processors中的主题 Re: EIM asynchronous multiplexed setup

EIM asynchronous multiplexed setup

pierreschirrer — Wed, 10 Oct 2012 16:00:20 GMT

Hello,

I am trying to setup the EIM of an i.MX53(MX535) to access both a Fujitsu FRAM (MB85R1002) and an FPGA. I cannot access either. The address bus is de-multiplexed by a 74LCX16373 transparent latch driven by EIM_CS0. I observe erratic address values on the address bus. The documentation is not helping much, there are no examples of asynchronous multiplexed timings in the reference manual.

Has anyone had luck in setting such a configuration up ?

For info, I tried the following setups, none work :

EIM_CS0WCR1 = 0x16002082, 0x16002682, 0x1F0C2E92

EIM_CS0RCR1 = 0x16000202 , 0x16000502, 0x1F034522

Regards.

Re: EIM asynchronous multiplexed setup

jimmychan — Wed, 31 Oct 2012 07:07:13 GMT

Would you mind to send me this part of schematic to review? If you don't want to show the schematic here, please submit a SR for this issue.

Re: EIM asynchronous multiplexed setup

pierreschirrer — Wed, 07 Nov 2012 08:08:00 GMT

Hello Jimmy, the confusion arose due to inconsistent documentation in the i.MX53 UG manual :

25.3.3 Multiplexed Address/Data Mode

In this mode, multiplexing addresses and data bits on the same pins is supported for

synchronous/asynchronous accesses to x8/x16/ x32 data width memory devices.

For more information about the pins that drive data/address in 8/16/32 non-muxed mode

and 16/32 muxed mode, refer to the EIM Internal Module Multiplexing table in the EIM

Internal Pads Allocation chapter of the datasheet.

In fact, do as you want, x8 bits mode does not work in multiplexed mode...

Regards.