topic Re: i.MX7 RMII 50MHz clock in i.MX Processors

i.MX7 RMII 50MHz clock

skrap — Tue, 02 Apr 2019 19:44:54 GMT

Hello,

I have read many entries on this forum about enabling a 50 MHz clock for use with a RMII ethernet PHY. I don't think I have anything special in my setup.

What I have noticed is that the clock is gated off at startup, and nothing ever enables it. This is on the rel_imx_4.9.88_2.0.0_ga kernel, plus the changes from toradex to set the enet1 ref clock output enable bit in the IOMUX GPR1.

After boot, communication via MDIO works, but the PHY doesn't see a link. Reading CCM_TARGET_ROOT78:

# devmem 0x3038A700
0x02000000

Note the enable bit (0x10000000) is off for ENET1_REF_CLK_ROOT.

If I turn it on:

# devmem 0x3038A700 32 0x12000000
fec 30be0000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready

Everything is great.

So, what is supposed to be ungating that clock? None of the devtree examples I have seen use it.

Any help would be appreciated!

Some reference links I have read:

RMII interface on the IMX7

How to output 50MHz on a pin of imx7d constantly

devtree is as follows:

&fec1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_enet1>;
    
    clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
        <&clks IMX7D_ENET_AXI_ROOT_CLK>,
        <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
        <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>,
        <&clks IMX7D_ENET1_REF_ROOT_CLK>;
        
    clock-names = "ipg", "ahb", "ptp",
        "enet_clk_ref", "enet_out";

    assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
             <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
    assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
    assigned-clock-rates = <0>, <100000000>;
    
    phy-mode = "rmii";
    phy-reset-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
    fsl,magic-packet;

    status = "okay";
};

Re: i.MX7 RMII 50MHz clock

igorpadykov — Wed, 03 Apr 2019 00:52:47 GMT

Hi Jonah

referenced links seems worked fine, why they are not suitable for your case, had you

tried with nxp linux releases from linux-imx - i.MX Linux kernel

Additionally ungating clock can be performed in uboot, for example in dcd header.

May be useful:

net: ethernet: fsl: don't en/disable refclk on open/close - Patchwork

Best regards
igor
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Re: i.MX7 RMII 50MHz clock

skrap — Wed, 03 Apr 2019 01:12:19 GMT

Hello Igor,

Is the bsp expecting that clock to be ungated in uboot? I have followed the solutions outlined in the referenced linked, but the enet reference clock isn't actually enabled when I get to a fully booted linux. I do see the clock come up for a short period during boot via the oscilloscope.

Re: i.MX7 RMII 50MHz clock

skrap — Wed, 03 Apr 2019 01:29:36 GMT

I just did review that discussion and diff, thank you for the link. I will try tomorrow to see if that patch helps, but I'm not clear on why it would be expected to help. But perhaps experimentation will reveal the answer? I'm still curious what the intended behavior of the BSP is for RMII. Should u-boot be responsible for enabling the clock?

Re: i.MX7 RMII 50MHz clock

skrap — Wed, 03 Apr 2019 12:50:28 GMT

Here's the problem: the BSP defines IMX7D_ENET1_REF_ROOT_CLK, but doesn't fill it in:

~/linux-imx$ git grep IMX7D_ENET1_REF_ROOT_CLK
include/dt-bindings/clock/imx7d-clock.h:#define IMX7D_ENET1_REF_ROOT_CLK 154

~/linux-imx$

When the FEC driver looks up the clock (when configured as in my devtree above) it is empty, the pointer is set to NULL, and so the clock is never ungated.

Re: i.MX7 RMII 50MHz clock

skrap — Wed, 03 Apr 2019 13:07:16 GMT

DuanFugang‌ This appears to have been broken by the following commit, which came in between the 4.1.15 and 4.9.88 NXP releases.

How shall the clock be enabled now, since IMX7D_ENET1_REF_ROOT_CLK is empty?

commit 1485e885e1169d93e5f2ceffadae14d1d434a940
Author: Andy Duan <fugang.duan@nxp.com>
Date: Fri Feb 10 16:25:14 2017 +0800

    MLK-13910: ARM: imx7d: clk: correct enet clock CCGR register offset

    Correct enet clock CCGR register offset.

    CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 enet2 bus clocks)
    CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
    CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK

    IMX7D_ENET_PHY_REF_ROOT_DIV supply clock for PHY, no gate after the clock, its parent
    clcok root has gate.
    IMX7D_ENET1_REF_ROOT_DIV/IMX7D_ENET2_REF_ROOT_DIV supply clocks for enet IPG_CLK_RMII,
    no gate after the clock, its parent clock root has gate.

    IMX7D_PLL_ENET_MAIN_125M_CLK (anatop pll) supply clock for enet RGMII tx_clk.

    Update copyright information.

    Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
    Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>

Re: i.MX7 RMII 50MHz clock

DuanFugang — Wed, 03 Apr 2019 14:03:11 GMT

Please note the commit log:

IMX7D_ENET1_REF_ROOT_DIV/IMX7D_ENET2_REF_ROOT_DIV supply clocks for enet IPG_CLK_RMII

So for your RMII 50Mhz clock, you should use IMX7D_ENET1_REF_ROOT_DIV/IMX7D_ENET2_REF_ROOT_DIV.

The clock tree:

IMX7D_PLL_ENET_MAIN_50M_CLK

IMX7D_ENET1_REF_ROOT_SRC

IMX7D_ENET1_REF_ROOT_CG

IMX7D_ENET1_REF_ROOT_PRE_DIV

IMX7D_ENET1_REF_ROOT_DIV

Re: i.MX7 RMII 50MHz clock

skrap — Wed, 03 Apr 2019 14:22:43 GMT

Thanks, that is helpful.

In the future, when changing a named clock like IMX7D_ENET1_REF_ROOT_CLK to become nonfunctional, it would be better to remove the IMX7D_ENET1_REF_ROOT_CLK symbol altogether, so that I get an error when compiling the devtree, rather than spending time debugging the kernel.

Alternatively, I suppose you could make IMX7D_ENET1_REF_ROOT_CLK an alias for IMX7D_ENET1_REF_ROOT_DIV.