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    <title>i.MX Processors中的主题 Re: i.MX8MMini(845s) FlexSPI NOR Flash Boot Question ?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8MMini-845s-FlexSPI-NOR-Flash-Boot-Question/m-p/869103#M132195</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Apollo&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for uuu example one cam look at uuu.fspi in&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com/webapp/Download?colCode=L4.9.123_2.3.0_8MM_GA&amp;amp;appType=license&amp;amp;location=null"&gt;Linux Binary Demo Files - i.MX 8MMini EVK&lt;/A&gt;&lt;/P&gt;&lt;P&gt;So one can try to build a FlexSPI imx-boot image using 4.9.123 GA or new&amp;nbsp;&amp;nbsp; L4.14.78&lt;BR /&gt;Yocto image and boot out of the Micron Quad NOR SPI on EVK.&amp;nbsp; Then apply the same &lt;BR /&gt;concepts and build the image for the custom flash.&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/support/developer-resources/software-development-tools/i.mx-developer-resources/i.mx-software-and-development-tool:IMX_SW" title="https://www.nxp.com/support/developer-resources/software-development-tools/i.mx-developer-resources/i.mx-software-and-development-tool:IMX_SW"&gt;i.MX Software | NXP&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Seems uboot FlexSPI driver uses some predefined luts based on JEDEC-standard JESD216B&lt;/P&gt;&lt;P&gt;using command "FSPI_CMD_RDID" Read JEDEC ID in uboot/drivers/spi/fsl_fspi.c&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://source.codeaurora.org/external/imx/uboot-imx/tree/drivers/spi/fsl_fspi.c?h=imx_v2018.03_4.14.78_1.0.0_ga" title="https://source.codeaurora.org/external/imx/uboot-imx/tree/drivers/spi/fsl_fspi.c?h=imx_v2018.03_4.14.78_1.0.0_ga"&gt;fsl_fspi.c\spi\drivers - uboot-imx - i.MX U-Boot&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 05 Mar 2019 08:17:33 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2019-03-05T08:17:33Z</dc:date>
    <item>
      <title>i.MX8MMini(845s) FlexSPI NOR Flash Boot Question ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8MMini-845s-FlexSPI-NOR-Flash-Boot-Question/m-p/869102#M132194</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We want to try to i.MX8MMini FlexSPI NOR flash Boot&lt;/P&gt;&lt;P&gt;But can't file LUT setting example file in UUU tool ?&lt;/P&gt;&lt;P&gt;And UUU example setting for burn FlexSPI NOR flash.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We can see example file (qspi-nor-micron-n25q256a-config , qspi-nor-micron-mt35xu512-config) in i.MX6UL / i.MX6ULL / i.MX7D MFG tool&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;i.MX6ULL LUT setting example&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*dqs_loopback=0 or 1*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*hold_delay=0 to 3*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*hsphs=0 (Half Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*hsdly=0 (Half Speed Delay one clk delay) or 1 (two clk cycle delay)*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*device_quad_mode_en=1 to enable sending command to SPI device*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*device_cmd=command to device for enableing Quad I/O mode*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*write_cmd_ipcr=hex value to be written to IPCR register for write cmd of device*/&lt;BR /&gt;2000000&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*write_enable_ipcr=hex value to be written to IPCR register for write enable of device*/&lt;BR /&gt;3&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*cs_hold_time=0 to 0xF*/&lt;BR /&gt;3&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*cs_setup_time=0 to 0xF*/&lt;BR /&gt;8000000&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*sflash_A1_size=size in byte(hex)*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*sflash_A2_size=size in byte(hex)*/&lt;BR /&gt;8000000&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*sflash_B1_size=size in byte(hex)*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*sflash_B2_size=size in byte(hex)*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*sclk_freq=0 to 6*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*busy_bit_offset=bit position of device BUSY in device status register*/&lt;BR /&gt;2&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*sflash_type=1 (Single), 2 (Dual), 4 (Quad mode of operation)*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*sflash_port=0 or 1 (Port B used)*/&lt;BR /&gt;1&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*ddr_mode_enable=0 or 1*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*dqs_enable=0 or 1*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*parallel_mode_enable=0 or 1*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*portA_cs1=0 or 1*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*portB_cs1=0 or 1*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*fsphs=0 (Full Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*fsdly=0 (Full Speed Delay One clk delay) or 1 (two clk cycle delay)*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*ddrsmp=0 to 7 (sampling point for incoming data in DDR mode)*/&lt;BR /&gt;2818043d&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*lut[0] command sequence*/&lt;BR /&gt;39040d06&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*lut[1] command sequence*/&lt;BR /&gt;2400&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*lut[2] command sequence*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*lut[3] command sequence*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*lut[4] command sequence*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*lut[5] command sequence*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*lut[6] command sequence*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*lut[7] command sequence*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*lut[8] command sequence*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*lut[9] command sequence*/&lt;BR /&gt;0&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;/*lut[10] command sequence*/&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 05 Mar 2019 07:27:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8MMini-845s-FlexSPI-NOR-Flash-Boot-Question/m-p/869102#M132194</guid>
      <dc:creator>Danube</dc:creator>
      <dc:date>2019-03-05T07:27:19Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8MMini(845s) FlexSPI NOR Flash Boot Question ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8MMini-845s-FlexSPI-NOR-Flash-Boot-Question/m-p/869103#M132195</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Apollo&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for uuu example one cam look at uuu.fspi in&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com/webapp/Download?colCode=L4.9.123_2.3.0_8MM_GA&amp;amp;appType=license&amp;amp;location=null"&gt;Linux Binary Demo Files - i.MX 8MMini EVK&lt;/A&gt;&lt;/P&gt;&lt;P&gt;So one can try to build a FlexSPI imx-boot image using 4.9.123 GA or new&amp;nbsp;&amp;nbsp; L4.14.78&lt;BR /&gt;Yocto image and boot out of the Micron Quad NOR SPI on EVK.&amp;nbsp; Then apply the same &lt;BR /&gt;concepts and build the image for the custom flash.&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/support/developer-resources/software-development-tools/i.mx-developer-resources/i.mx-software-and-development-tool:IMX_SW" title="https://www.nxp.com/support/developer-resources/software-development-tools/i.mx-developer-resources/i.mx-software-and-development-tool:IMX_SW"&gt;i.MX Software | NXP&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Seems uboot FlexSPI driver uses some predefined luts based on JEDEC-standard JESD216B&lt;/P&gt;&lt;P&gt;using command "FSPI_CMD_RDID" Read JEDEC ID in uboot/drivers/spi/fsl_fspi.c&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://source.codeaurora.org/external/imx/uboot-imx/tree/drivers/spi/fsl_fspi.c?h=imx_v2018.03_4.14.78_1.0.0_ga" title="https://source.codeaurora.org/external/imx/uboot-imx/tree/drivers/spi/fsl_fspi.c?h=imx_v2018.03_4.14.78_1.0.0_ga"&gt;fsl_fspi.c\spi\drivers - uboot-imx - i.MX U-Boot&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 05 Mar 2019 08:17:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8MMini-845s-FlexSPI-NOR-Flash-Boot-Question/m-p/869103#M132195</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-03-05T08:17:33Z</dc:date>
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