topic IMX8M MIPI-CSI Host Controller: send level? in i.MX Processors

IMX8M MIPI-CSI Host Controller: send level?

john_obendorfer — Fri, 25 Jan 2019 19:11:40 GMT

In the driver mxc-mipi-csi2_yav.c, there's a point the function mxc_mipi_csi2_hc_config() where a parameter called "send level" is written to an undocumented register at offset 0188H from the base of the host controller register file.

The value 1 is also written to an undocumented register at offset 0180H and 0184H.

Can anyone tell me what these settings do, and how they were derived?

Re: IMX8M MIPI-CSI Host Controller: send level?

Yuri — Fri, 08 Feb 2019 07:50:51 GMT

Hello,

Appears, some details of the CSI I/F are missed in the Reference Manual (RM).

Customers may need wait for the next update of the RM. I do not have

exact schedule for new RM issue.

The send level configures the number of entries that must accumulate in the Pixel FIFO

before the data will be transferred to the video output. The exact value needed for this configuration

is dependent on the rate at which the sensor transfers data to the CSI-2 Controller and the user

video clock.

The offset 0180H, bit 0: when set - the interface ignores the Virtual Channel (VC) field in received packets.
When clear - this causes the interface to only accept packets whose VC matches the value to which VC

is set in the offset 0184H.

Have a great day,

Yuri

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Re: IMX8M MIPI-CSI Host Controller: send level?

koki_sato — Tue, 03 Mar 2020 08:50:28 GMT

How to calculate "send_level", which is a sensor rate dependent value?

Re: IMX8M MIPI-CSI Host Controller: send level?

Yuri — Wed, 08 Apr 2020 06:10:42 GMT

Hello,

"The calculation is the classical rate in rate out type of problem. If the video bandwidth is 10% faster

than the incoming mipi data and the video line length is 500 pixels, then the fifo should be allowed to fill

to 10% of the line length or 50 pixels or so.

Again, if the gap data is ok, then the level can be set to 16 and ignored"

Regards,

Yuri.