i.MX ProcessorsのトピックRe: how does rpmsg on imx6sx work?

how does rpmsg on imx6sx work?

jingyangxie — Mon, 04 Mar 2019 04:49:44 GMT

I have an imx6sx motherboard, use rpmsg for A9 and M4 communication. When A9 sends data to M4 for 256 times, each time M4 can receive the correct data, but when it reaches the 257th time, the data received by M4 is the same with the first one. why is this?

PS:

M4 freertos 1.0.1

A9:linux 4.1.15

Re: how does rpmsg on imx6sx work?

art — Mon, 11 Mar 2019 07:56:03 GMT

To make me able to accurately study the case, please describe in details and step by step, what exactly i.MX6SoloX hardware do you use (is it the i.MX6SX SABRE SD board or your own custom hardware?), what application software do you run on both A9 and M4 cores, how do you perform the test, what do you expect and what results do you actually get.

In general, the most likely cause of the issue is that the M4 core does not flush its rpmsg receive queue somehow.

Have a great day,
Artur

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Re: how does rpmsg on imx6sx work?

jingyangxie — Mon, 11 Mar 2019 09:09:18 GMT

Hi, Artur

I have a custom board which copy form I.MX6SX SABRE SD borad,M4 run the "str_echo_bm" demo and modify the data format, from receiving the string to receiving the int value, then the program run by A9 is an infinite loop function, each time sending 100 int values, then M4 prints the first and last values ,when the number of times sent to M4 exceeds 256 times, the values of the first and last outputs of the M4 are different, and some data is similar with the first time.

Re: how does rpmsg on imx6sx work?

art — Mon, 11 Mar 2019 09:58:47 GMT

It still mostly looks like the software issue. Please double-check that the M4 code actually reads all received data from the Message Unit Receive registers on the M4 core side.

Best Regards,

Artur

Re: how does rpmsg on imx6sx work?

jingyangxie — Thu, 14 Mar 2019 02:56:30 GMT

Hi,Artur

Could you give me any tips ? How can I check Message Unit Receive registers on the M4 core side?

Re: how does rpmsg on imx6sx work?

art — Thu, 14 Mar 2019 08:21:42 GMT

Double-check that each time the M4 side of the Message Unit hardware receives a message, the code, running on the M4 core, explicitly reads it.