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    <title>topic Re: DRAM Contoroller Optimization and Pattern Simulation for DDR3 and EMMC in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/DRAM-Contoroller-Optimization-and-Pattern-Simulation-for-DDR3/m-p/860962#M131385</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello JA,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If the only change on the PCB is the swap from i.MX6D to the i.MX6Q, you may use the optimization you already have. However, it’s always a practice to perform some stress tests to make sure there are no other variables like manufacturing variations involved as well.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope this helps!&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 25 Jan 2019 22:15:00 GMT</pubDate>
    <dc:creator>gusarambula</dc:creator>
    <dc:date>2019-01-25T22:15:00Z</dc:date>
    <item>
      <title>DRAM Contoroller Optimization and Pattern Simulation for DDR3 and EMMC</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DRAM-Contoroller-Optimization-and-Pattern-Simulation-for-DDR3/m-p/860961#M131384</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We are currently using i.MX6 Dual.&amp;nbsp;&lt;/P&gt;&lt;P&gt;But if i.MX6 Dual is replaced with i.MX6 Quad on the same PCB,&amp;nbsp;is DRAM&amp;nbsp;Controller Optimization needed to re-generate again for i.MX6 Quad?&lt;/P&gt;&lt;P&gt;Or can we re-use&amp;nbsp;the one of i.MX6 Dual&amp;nbsp;against the one of i.MX6 Quad?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR,&lt;/P&gt;&lt;P&gt;JA&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 25 Jan 2019 02:20:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DRAM-Contoroller-Optimization-and-Pattern-Simulation-for-DDR3/m-p/860961#M131384</guid>
      <dc:creator>asou_junichi</dc:creator>
      <dc:date>2019-01-25T02:20:19Z</dc:date>
    </item>
    <item>
      <title>Re: DRAM Contoroller Optimization and Pattern Simulation for DDR3 and EMMC</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DRAM-Contoroller-Optimization-and-Pattern-Simulation-for-DDR3/m-p/860962#M131385</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello JA,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If the only change on the PCB is the swap from i.MX6D to the i.MX6Q, you may use the optimization you already have. However, it’s always a practice to perform some stress tests to make sure there are no other variables like manufacturing variations involved as well.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope this helps!&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 25 Jan 2019 22:15:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DRAM-Contoroller-Optimization-and-Pattern-Simulation-for-DDR3/m-p/860962#M131385</guid>
      <dc:creator>gusarambula</dc:creator>
      <dc:date>2019-01-25T22:15:00Z</dc:date>
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