topic Re: a question about IMX8QXP eDMA in i.MX Processors

a question about IMX8QXP eDMA

jun_li1 — Thu, 28 Mar 2019 07:58:07 GMT

In IMX8DQXPRM(Rev.D 11/2018).pdf I saw register memory map list as below:

This is register map of eDMA in Connectivity subsystem.

My questions are:

a.I can NOT see which peripherals associated with those 5 Connectivity's eDMA channels.

b.What the difference between Connectivity's eDMA and ADMA's eDMAs?

c.If I want to access ADMA's eDMA controller register(0x5a1f0000), which clock domain and gates need to be enabled? now I can access ADMA's eDMA's channel register, but cannot access ADMA's eDMA controller register.

d.Can all those channels perform moving data from memory to memory?

Re: a question about IMX8QXP eDMA

igorpadykov — Fri, 29 Mar 2019 01:44:47 GMT

Hi Li

a. one can look at Figure 16-1. Audio Subsystem High-Level Block Diagram,

Table 16-2. eDMAn Channel Map i.MX8QXP Reference Manual

https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf

b. one can look at architecture description in Figure 1-1. i.MX 8QuadXPlus/i.MX 8DualXPlus

Simplified Block Diagram, Chapter 14 Connectivity Subsystem

c. for eDMA2((0x5a1f0000) one can check clock control LPCG_EDMA2 descriptions

in Table 8-4. System Clocks, and Gating, sect.8.4 Low Power Clock Gating Control

d. yes

Best regards
igor
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Re: a question about IMX8QXP eDMA

jun_li1 — Fri, 29 Mar 2019 04:31:50 GMT

Hi Igor,

Thanks for your quick reply.

I also have something else not clear:

a.I can see the details about Audio Subsystem eDMA controllers eDMA0~3, but nothing about Connectivity eDMA controller(may be could called eDMA4). Does eDMA4 (0x5b070000~0x5b0cffff) work? Is there no peripherals be associated with those 5 channels?

c. I still meet: In Connectivity, LPCG_EDMA_REGS (0x5b2a0000) can NOT access, but LPCG_RAWNAND_0_REGS(0x5b290000) could.

Re: a question about IMX8QXP eDMA

igorpadykov — Fri, 29 Mar 2019 07:19:45 GMT

Hi Li

a. "Connectivity Subsystem" is just another module which has own eDMA module.

> Is there no peripherals be associated with those 5 channels?

please check Figure 14-1. Simplified Block Diagram in Chapter 14
Connectivity Subsystem Reference Manual.

b. one can check eDMA examples in SDK for i.MX 8QuadXPlus (SDK_2.5.0_MEK-MIMX8QX)

available on

Welcome | MCUXpresso SDK Builder

For specific issues with eDMA development may be recommended to proceed with

NXP Professional Services | NXP

Note this part is "Preproduction" as described in red on below link - so there no full support for it.

i.MX 8X Applications Processors| Arm® Cortex®-A35, Cortex-M4 | NXP

Best regards
igor