i.MX Processors中的主题 Re: Memory bandwidth saving for IPU processing

Memory bandwidth saving for IPU processing

Kazuma_Sasaki — Mon, 07 Jan 2019 10:27:48 GMT

Our system could not play the video normally. It seems that lack of memory bandwidth for our usage.

Therefore, we would like to reduce memory traffic between IPU and DRAM.

I have two ideas to reduce memory traffic after checked reference manual and community.

Is it available on i.MX6 platform? if it is not available or you know more suitable solutions, please give us any advice.

<Current data flow> data traffic between IPU and DRAM = 1920 x 1080 x 3byte per pixel x 2times = 11.86MB / frame

Input case :

Video source(YUV422 720x480) -> CSI -> IC (CSC YUV422 to RGB24 and resizing to 1920x1080) -(IDMAC ch0)-> DRAM

Output case :

DRAM -(IDMAC ch23)->DMFC->DP->DC->DI->Monitor(RGB24 1920x1080)

#1 CSC moving to DP

We expect data traffic reduce as below by CSC moving to DP.

data traffic between IPU and DRAM = 1920 x 1080 x 2byte per two pixels x 2times = 3.95MB / frame

Input case :

Video source(YUV422 720x480) -> CSI -> IC (resizing to 1920x1080) -(IDMAC ch0)-> DRAM

Output case :

DRAM -(IDMAC ch23)->DMFC->DP(CSC YUV422 to RGB24)->DC->DI->Monitor(RGB24 1920x1080)

#2 video data directory transfer IC to DMFC

We expect data traffic reduce to 0 byte. but, I am not sure following flow is available or not.

Input case :

Video source(YUV422 720x480) -> CSI -> IC (CSC YUV422 to RGB24 and resizing to 1920x1024) -(IDMAC ch21)-> DMFC

Output case :

DMFC->DP->DC->DI->Monitor(RGB24 1920x1024)

<Note>

I checked following threads :

A Deep Dive into Image Processing for i.MX 6 Series Applications Processors

Best Regards,

Kazuma Sasaki.

Re: Memory bandwidth saving for IPU processing

igorpadykov — Thu, 10 Jan 2019 10:55:03 GMT

Hi Kazuma

in general it makes sense to perform CSC in DP as DP has better CSC performance.

Seems for case 2 DFMC can not be routed to DP, as according to IC chapter
sect.37.4.5.4 Main Processing Section i.MX6DQ Reference Manual :
"The IDMAC transfers the output bursts to the system memory or to the display via
DMFC (Channel 21only)" and it stated in Table 37-23. Display port channels):
"This channel can be routed to the DC channels 1,2,5B,5F,6B,6F.

http://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf

Best regards
igor
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Re: Memory bandwidth saving for IPU processing

Kazuma_Sasaki — Fri, 11 Jan 2019 11:45:22 GMT

Hi Igor,

I appreciate your support. Let me confirm two things about your answer.

Q1. You meant we can route following path?

Input case :

Video source(YUV422 720x480) -> CSI -> IC (CSC YUV422 to RGB24 and resizing to 1920x1024) -(IDMAC ch21)-> DMFC

Output case :

DMFC->DC->DI->Monitor(RGB24 1920x1024)

Q2. If above path is ok, IC can send to data more than 1024 pixels to DMFC?

We would like to use this solution for displaying FullHD contents. it is necessary 1080 pixels send from IC to DMFC.

Best Regards,

Kazuma Sasaki.

Re: Memory bandwidth saving for IPU processing

igorpadykov — Fri, 11 Jan 2019 12:00:42 GMT

Hi Kazuma

seems path (Q1) is feasible.

There are still 1024 restrictions (as for example resize) for IC operations,

for sending operations it can operate data more than 1024 pixels.

Best regards
igor