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    <title>topic i.MX6SDL  Multi-mode DDR controller(MMDC) in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6SDL-Multi-mode-DDR-controller-MMDC/m-p/853699#M130545</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P style="padding: 0px; min-height: 8pt;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I would like to ask about MMDC&amp;nbsp;feature.&lt;/P&gt;&lt;P&gt;MMDC supports up to 4 GByte DDR memory space.&lt;/P&gt;&lt;P&gt;Does this feature mean 1 CS channel&amp;nbsp;has &amp;nbsp;4 GByte address&amp;nbsp;space?&lt;/P&gt;&lt;DIV&gt;&lt;SPAN&gt;&lt;SPAN title=""&gt;It is described in the Reference Manual&amp;nbsp; "For LPDDR2 2ch x32 up to 2 GB per channel"&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&lt;SPAN title=""&gt;Does&amp;nbsp;it&amp;nbsp;mean for LPDDR2 supports up to 4 GByte DDR memory space by 2 CS?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;P style="padding: 0px; min-height: 8pt;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 27 Feb 2019 10:50:48 GMT</pubDate>
    <dc:creator>hirosuzu</dc:creator>
    <dc:date>2019-02-27T10:50:48Z</dc:date>
    <item>
      <title>i.MX6SDL  Multi-mode DDR controller(MMDC)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6SDL-Multi-mode-DDR-controller-MMDC/m-p/853699#M130545</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P style="padding: 0px; min-height: 8pt;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I would like to ask about MMDC&amp;nbsp;feature.&lt;/P&gt;&lt;P&gt;MMDC supports up to 4 GByte DDR memory space.&lt;/P&gt;&lt;P&gt;Does this feature mean 1 CS channel&amp;nbsp;has &amp;nbsp;4 GByte address&amp;nbsp;space?&lt;/P&gt;&lt;DIV&gt;&lt;SPAN&gt;&lt;SPAN title=""&gt;It is described in the Reference Manual&amp;nbsp; "For LPDDR2 2ch x32 up to 2 GB per channel"&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&lt;SPAN title=""&gt;Does&amp;nbsp;it&amp;nbsp;mean for LPDDR2 supports up to 4 GByte DDR memory space by 2 CS?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;P style="padding: 0px; min-height: 8pt;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 27 Feb 2019 10:50:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6SDL-Multi-mode-DDR-controller-MMDC/m-p/853699#M130545</guid>
      <dc:creator>hirosuzu</dc:creator>
      <dc:date>2019-02-27T10:50:48Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6SDL  Multi-mode DDR controller(MMDC)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6SDL-Multi-mode-DDR-controller-MMDC/m-p/853700#M130546</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi HIROYUKI&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for MMDC supported configurations one can check&lt;/P&gt;&lt;P&gt;sect.2.3 DDR mapping to MMDC controller ports i.MX6SDL Reference Manual&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6SDLRM.pdf" title="http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6SDLRM.pdf"&gt;http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6SDLRM.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 27 Feb 2019 23:32:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6SDL-Multi-mode-DDR-controller-MMDC/m-p/853700#M130546</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-02-27T23:32:35Z</dc:date>
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