topic Re: PD/PU resistor values on GPIO of i.MX8M in i.MX Processors

PD/PU resistor values on GPIO of i.MX8M

Norihiro — Tue, 26 Mar 2019 10:08:13 GMT

Hello,

In IMX8MDQLQIEC, there are two different number for PD/PU resistor values.

Table 26 says,

30 x 0.75 Kohms (min) , 30 Kohms(typ), 30 x 1.25 Kohms(max.) for PU.

95 x 0.75 Kohms (min) , 95Kohms(typ), 95 x 1.25 Kohms(max) for PD.

Table 84 says

90 Kohms(PD)

27 Kohms(PU)

** It says GPIO1_IO02 has 27Kohms PD. It seems to be typo.

If the table 84 refers to typ value in Table 26, it make sense.

I understand that PU/PD on silicon are not so accurate, so these small difference doesn't matter for NXP.

But the values should be the same and consistent to avoid confusion at your customer's site.

Can we take PD/PU resistor value in Table 26 as your authorized value?

Thanks,

Norihiro Michigami

AVNET

Re: PD/PU resistor values on GPIO of i.MX8M

Yuri — Wed, 27 Mar 2019 04:20:55 GMT

Hello,

The Datasheet table 26 (GPIO DC parameters) is correct regarding pull-up resistor 30K +/- 0.25K

and pull-down resistor 95K +/- 0.25K.

As for the GPIO1_IO02: customers can use IOMUXC registers, in particular -

IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 - to define what pins have internal 27K Ohm

pull up resistor enabled. The bit PUE of IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 is set.

Note, i.MX8M GPIOs have internal PD(90K), which can’t be disabled

Have a great day,
Yuri

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

Re: PD/PU resistor values on GPIO of i.MX8M

Norihiro — Thu, 28 Mar 2019 04:56:05 GMT

Hello Yuri,

Thank you for your reply.

I understood that default value of PUE bit for IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 is enabled whereas

PUE for other GPIO is disabled basically.

Thanks,

Norihiro Michigami

AVNET