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    <title>i.MX Processors中的主题 Does EIM support the old Intel Multiplex operation mode</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Does-EIM-support-the-old-Intel-Multiplex-operation-mode/m-p/849194#M129966</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have a device that I would like to connect to my iMX6-DL via a parallel interface using the EIM module. This device is rather old and supports 10 MHz interfaces using "Motorola", "Intel", or "Intel Multiplexed" pin schema.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;To reduce pin count, I would like to use the "Intel Multiplexed" mode. I see that the EIM supports multiplexed address/data but do not see anything like ALE functionality in the EIM description. (The EIM_LBA is active low and I do not see it deasserting before CS assertion.)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does anyone know if the EIM can support this functionality? If so, is there a data sheet that describes the timing of this interface?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&amp;nbsp;&lt;/P&gt;&lt;P&gt;Doug Bailey&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 24 Jul 2018 16:51:55 GMT</pubDate>
    <dc:creator>dougbailey</dc:creator>
    <dc:date>2018-07-24T16:51:55Z</dc:date>
    <item>
      <title>Does EIM support the old Intel Multiplex operation mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Does-EIM-support-the-old-Intel-Multiplex-operation-mode/m-p/849194#M129966</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have a device that I would like to connect to my iMX6-DL via a parallel interface using the EIM module. This device is rather old and supports 10 MHz interfaces using "Motorola", "Intel", or "Intel Multiplexed" pin schema.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;To reduce pin count, I would like to use the "Intel Multiplexed" mode. I see that the EIM supports multiplexed address/data but do not see anything like ALE functionality in the EIM description. (The EIM_LBA is active low and I do not see it deasserting before CS assertion.)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does anyone know if the EIM can support this functionality? If so, is there a data sheet that describes the timing of this interface?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&amp;nbsp;&lt;/P&gt;&lt;P&gt;Doug Bailey&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 24 Jul 2018 16:51:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Does-EIM-support-the-old-Intel-Multiplex-operation-mode/m-p/849194#M129966</guid>
      <dc:creator>dougbailey</dc:creator>
      <dc:date>2018-07-24T16:51:55Z</dc:date>
    </item>
    <item>
      <title>Re: Does EIM support the old Intel Multiplex operation mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Does-EIM-support-the-old-Intel-Multiplex-operation-mode/m-p/849195#M129967</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Dough&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;EIM_LBA timings are configured with RADVA and RADVN fields of the EIM_CSxRCR1 register,&lt;/P&gt;&lt;P&gt;RCSA and RCSN configures CS timings.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 24 Jul 2018 23:36:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Does-EIM-support-the-old-Intel-Multiplex-operation-mode/m-p/849195#M129967</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-07-24T23:36:53Z</dc:date>
    </item>
    <item>
      <title>Re: Does EIM support the old Intel Multiplex operation mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Does-EIM-support-the-old-Intel-Multiplex-operation-mode/m-p/849196#M129968</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;So other than the polarity of the LBA signal i.e. it asserts low when address is valid while the ALE signal on an Intel Muxed interface asserts high, I should be able to configure the RADVA, RADVN, RCSA, and RCSN value to output a waveform for a read. &amp;nbsp;Similarly, the W&lt;SPAN&gt;ADVA, WADVN, WCSA, and WCSN can be configured for a write.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks for the information.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Regards,&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Doug&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Jul 2018 14:13:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Does-EIM-support-the-old-Intel-Multiplex-operation-mode/m-p/849196#M129968</guid>
      <dc:creator>dougbailey</dc:creator>
      <dc:date>2018-07-25T14:13:40Z</dc:date>
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