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    <title>i.MX ProcessorsのトピックRe: imx6q IPU2 CSI1 timeout</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx6q-IPU2-CSI1-timeout/m-p/847501#M129754</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;It works.&lt;/P&gt;&lt;P&gt;It was an electric problem.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Solved !&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 12 Oct 2018 19:22:00 GMT</pubDate>
    <dc:creator>Rbe78</dc:creator>
    <dc:date>2018-10-12T19:22:00Z</dc:date>
    <item>
      <title>imx6q IPU2 CSI1 timeout</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6q-IPU2-CSI1-timeout/m-p/847499#M129752</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We tried to use IPU2 CSI1 with an ADV7182 on imx6q variscite dart.&lt;/P&gt;&lt;P&gt;We compiled yocto krogoth.&lt;/P&gt;&lt;P&gt;Modules activated :&lt;/P&gt;&lt;P&gt;CONFIG_MXC_TVIN_ADV7180&lt;BR /&gt;CONFIG_VIDEO_MXC_CAPTURE&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;dtb :&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;TABLE class="j-table jiveBorder" style="border: 1px solid #c6c6c6;" width="100%"&gt;&lt;THEAD&gt;&lt;TR style="background-color: #efefef;"&gt;&lt;TH&gt;&lt;SPAN style="font-weight: 400;"&gt;In iomux section&lt;/SPAN&gt;&lt;/TH&gt;&lt;/TR&gt;&lt;/THEAD&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD&gt;&lt;P&gt;pinctrl_ipu2: ipu2grp { /* parallel port 16-bit */&lt;BR /&gt; fsl,pins = &amp;lt;&lt;/P&gt;&lt;P&gt;MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1&lt;BR /&gt; MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1&lt;BR /&gt; MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1&lt;BR /&gt; MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1&lt;BR /&gt; MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1&lt;BR /&gt; MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1&lt;BR /&gt; MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1&lt;BR /&gt; MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0xb0b1&lt;BR /&gt; MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1&lt;BR /&gt; MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0xb0b1 /* remove this line has no effect */&lt;BR /&gt; MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1&lt;BR /&gt; MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1&lt;BR /&gt; &amp;gt;;&lt;BR /&gt; };&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;TABLE class="j-table jiveBorder" style="border: 1px solid #c6c6c6;" width="100%"&gt;&lt;THEAD&gt;&lt;TR style="background-color: #efefef;"&gt;&lt;TH&gt;&lt;SPAN style="font-weight: 400;"&gt;In i2c section&lt;/SPAN&gt;&lt;/TH&gt;&lt;/TR&gt;&lt;/THEAD&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD&gt;&lt;SPAN&gt;adv7180: adv7180@20 {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;compatible = "adv,adv7180";&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;reg = &amp;lt;0x20&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;pinctrl-names = "default";&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_ipu2&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;clocks = &amp;lt;&amp;amp;clks 201&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;clock-names = "csi_mclk";&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DOVDD-supply = &amp;lt;&amp;amp;reg_3p3v&amp;gt;; /* 3.3v, enabled via 2.8 VGEN6 */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;AVDD-supply = &amp;lt;&amp;amp;reg_3p3v&amp;gt;; /* 1.8v */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DVDD-supply = &amp;lt;&amp;amp;reg_3p3v&amp;gt;; /* 1.8v */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;PVDD-supply = &amp;lt;&amp;amp;reg_3p3v&amp;gt;; /* 1.8v */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;pwn-gpios = &amp;lt;&amp;amp;gpio4 21 0&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;ipu_id = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;csi_id = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;mclk = &amp;lt;24000000&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;mclk_source = &amp;lt;0&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;cvbs = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&lt;/P&gt;&lt;TABLE class="j-table jiveBorder" style="border: 1px solid #c6c6c6;" width="100%"&gt;&lt;THEAD&gt;&lt;TR style="background-color: #efefef;"&gt;&lt;TH&gt;&lt;SPAN style="font-weight: 400;"&gt;in / section&lt;/SPAN&gt;&lt;/TH&gt;&lt;/TR&gt;&lt;/THEAD&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD&gt;&lt;P style="padding: 0px;"&gt;v4l2_cap_0 {&lt;BR /&gt;compatible = "fsl,imx6q-v4l2-capture";&lt;BR /&gt;ipu_id = &amp;lt;1&amp;gt;;&lt;BR /&gt;csi_id = &amp;lt;1&amp;gt;;&lt;BR /&gt;mclk_source = &amp;lt;0&amp;gt;;&lt;BR /&gt;status = "okay";&lt;BR /&gt;};&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There are&amp;nbsp; no io conflicts.&lt;/P&gt;&lt;P&gt;The&amp;nbsp;&lt;SPAN&gt;IPU2_CSI1_DATA_EN is pulled down at startup and connected to another cpu's io.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Change io level has no effect.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;TABLE class="j-table jiveBorder" style="border: 1px solid #c6c6c6;" width="100%"&gt;&lt;THEAD&gt;&lt;TR style="background-color: #efefef;"&gt;&lt;TH&gt;#&amp;nbsp;&lt;SPAN style="font-weight: 400;"&gt;cat /dev/video0&lt;/SPAN&gt;&lt;/TH&gt;&lt;/TR&gt;&lt;/THEAD&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD&gt;prp_still_start: ipu_channel_request still 1 1&lt;BR /&gt;ERROR: v4l2 capture: mxc_v4l_read timeout counter 0&lt;BR /&gt;cat: read error: Timer expired&lt;BR /&gt;root@var-som-mx6:~# dmesg&lt;BR /&gt;adv7180 0-0020: adv7180:ioctl_g_ifparm&lt;BR /&gt;adv7180 0-0020: adv7180:ioctl_g_fmt_cap&lt;BR /&gt; Returning size of 720x625&lt;BR /&gt;imx-ipuv3 2800000.ipu: CSI_SENS_CONF = 0x80000A02&lt;BR /&gt;imx-ipuv3 2800000.ipu: CSI_ACT_FRM_SIZE = 0x027002CF&lt;BR /&gt;adv7180 0-0020: adv7180:ioctl_s_power&lt;BR /&gt;adv7180 0-0020: In adv7180:ioctl_init&lt;BR /&gt;adv7180 0-0020: adv7180:ioctl_dev_init&lt;BR /&gt;prp_still_start: ipu_channel_request still 1 1&lt;BR /&gt;imx-ipuv3 2800000.ipu: init channel = 15&lt;BR /&gt;imx-ipuv3 2800000.ipu: ipu busfreq high requst.&lt;BR /&gt;imx-ipuv3 2800000.ipu: initializing idma ch 0 @ c0980000&lt;BR /&gt;imx-ipuv3 2800000.ipu: ch 0 word 0 - 00000000 0C600000 0003DE00 E0000000 00057C23&lt;BR /&gt;imx-ipuv3 2800000.ipu: ch 0 word 1 - 07840000 00F09000 0047C000 000047C0 0000008F&lt;BR /&gt;imx-ipuv3 2800000.ipu: PFS 0x2,&lt;BR /&gt;imx-ipuv3 2800000.ipu: BPP 0x0,&lt;BR /&gt;imx-ipuv3 2800000.ipu: NPB 0x1f&lt;BR /&gt;imx-ipuv3 2800000.ipu: FW 287,&lt;BR /&gt;imx-ipuv3 2800000.ipu: FH 351,&lt;BR /&gt;imx-ipuv3 2800000.ipu: EBA0 0x3c200000&lt;BR /&gt;imx-ipuv3 2800000.ipu: EBA1 0x3c240000&lt;BR /&gt;imx-ipuv3 2800000.ipu: Stride 287&lt;BR /&gt;imx-ipuv3 2800000.ipu: scan_order 0&lt;BR /&gt;imx-ipuv3 2800000.ipu: uv_stride 143&lt;BR /&gt;imx-ipuv3 2800000.ipu: u_offset 0x18c00&lt;BR /&gt;imx-ipuv3 2800000.ipu: v_offset 0x1ef00&lt;BR /&gt;imx-ipuv3 2800000.ipu: Width0 0+1,&lt;BR /&gt;imx-ipuv3 2800000.ipu: Width1 0+1,&lt;BR /&gt;imx-ipuv3 2800000.ipu: Width2 0+1,&lt;BR /&gt;imx-ipuv3 2800000.ipu: Width3 0+1,&lt;BR /&gt;imx-ipuv3 2800000.ipu: Offset0 15,&lt;BR /&gt;imx-ipuv3 2800000.ipu: Offset1 4,&lt;BR /&gt;imx-ipuv3 2800000.ipu: Offset2 0,&lt;BR /&gt;imx-ipuv3 2800000.ipu: Offset3 0&lt;BR /&gt;ERROR: v4l2 capture: mxc_v4l_read timeout counter 0&lt;BR /&gt;imx-ipuv3 2800000.ipu: CSI stop timeout - 5 * 10ms&lt;BR /&gt;imx-ipuv3 2800000.ipu: ipu busfreq high release.&lt;BR /&gt;adv7180 0-0020: adv7180:ioctl_s_power&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;TABLE class="j-table jiveBorder" style="border: 1px solid #c6c6c6;" width="100%"&gt;&lt;THEAD&gt;&lt;TR style="background-color: #efefef;"&gt;&lt;TH&gt;#&amp;nbsp;&lt;SPAN style="font-weight: 400;"&gt;cat /proc/interrupts&lt;/SPAN&gt;&lt;/TH&gt;&lt;/TR&gt;&lt;/THEAD&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD&gt;CPU0 CPU1 CPU2 CPU3&lt;BR /&gt; 16: 5504 2740 1398 295 GIC 29 Edge twd&lt;BR /&gt; 17: 97575 0 0 0 GPC 55 Level i.MX Timer Tick&lt;BR /&gt; 24: 3515 0 0 0 GPC 26 Level 2020000.serial&lt;BR /&gt; 25: 0 0 0 0 GPC 47 Level 202c000.ssi&lt;BR /&gt; 26: 0 0 0 0 GPC 50 Level 2034000.asrc&lt;BR /&gt; 27: 0 0 0 0 GPC 3 Edge VPU_JPG_IRQ&lt;BR /&gt; 28: 0 0 0 0 GPC 12 Level VPU_CODEC_IRQ&lt;BR /&gt; 39: 0 0 0 0 gpio-mxc 6 Edge 2194000.usdhc cd&lt;BR /&gt;160: 0 0 0 0 gpio-mxc 25 Edge Menu&lt;BR /&gt;161: 0 0 0 0 gpio-mxc 26 Edge Back&lt;BR /&gt;180: 0 0 0 0 gpio-mxc 11 Edge Home&lt;BR /&gt;269: 0 0 0 0 GPC 80 Level 20bc000.wdog&lt;BR /&gt;272: 0 0 0 0 GPC 49 Level imx_thermal&lt;BR /&gt;277: 0 0 0 0 GPC 19 Level rtc alarm&lt;BR /&gt;278: 0 0 0 0 GPC 4 Level 20cc000.snvs:snvs-powerkey&lt;BR /&gt;285: 0 0 0 0 GPC 2 Level sdma&lt;BR /&gt;286: 144 0 0 0 GPC 43 Level 2184000.usb&lt;BR /&gt;287: 1731 0 0 0 GPC 40 Level 2184200.usb&lt;BR /&gt;288: 64 0 0 0 GPC 118 Level 2188000.ethernet&lt;BR /&gt;289: 0 0 0 0 GPC 119 Level 2188000.ethernet&lt;BR /&gt;290: 147 0 0 0 GPC 22 Level mmc0&lt;BR /&gt;291: 0 0 0 0 GPC 23 Level mmc1&lt;BR /&gt;292: 1437 0 0 0 GPC 24 Level mmc2&lt;BR /&gt;293: 766 0 0 0 GPC 36 Level 21a0000.i2c&lt;BR /&gt;294: 176 0 0 0 GPC 37 Level 21a4000.i2c&lt;BR /&gt;295: 2 0 0 0 GPC 38 Level 21a8000.i2c&lt;BR /&gt;299: 0 0 0 0 GPC 18 Level vdoa&lt;BR /&gt;300: 0 0 0 0 GPC 27 Level 21e8000.serial&lt;BR /&gt;301: 0 0 0 0 GPC 28 Level 21ec000.serial&lt;BR /&gt;302: 4 0 0 0 GPC 6 Level 2400000.ipu&lt;BR /&gt;303: 0 0 0 0 GPC 5 Level 2400000.ipu&lt;BR /&gt;304: 0 0 0 0 GPC 107 Level mmdc_1&lt;BR /&gt;305: 0 0 0 0 GPC 112 Level mmdc_1&lt;BR /&gt;306: 0 0 0 0 GPC 113 Level mmdc_1&lt;BR /&gt;307: 0 0 0 0 GPC 114 Level mmdc_1&lt;BR /&gt;311: 0 0 0 0 GPC 8 Level 2800000.ipu&lt;BR /&gt;312: 0 0 0 0 GPC 7 Level 2800000.ipu&lt;BR /&gt;313: 2 0 0 0 GIC 137 Level 2101000.jr0&lt;BR /&gt;314: 0 0 0 0 GIC 138 Level 2102000.jr1&lt;BR /&gt;IPI0: 0 0 0 0 CPU wakeup interrupts&lt;BR /&gt;IPI1: 0 43648 4490 188 Timer broadcast interrupts&lt;BR /&gt;IPI2: 8650 14077 13812 16788 Rescheduling interrupts&lt;BR /&gt;IPI3: 20 24 26 17 Function call interrupts&lt;BR /&gt;IPI4: 4 10 1 0 Single function call interrupts&lt;BR /&gt;IPI5: 0 0 0 0 CPU stop interrupts&lt;BR /&gt;IPI6: 1 0 0 0 IRQ work interrupts&lt;BR /&gt;IPI7: 0 0 0 0 completion interrupts&lt;BR /&gt;Err: 0&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;We tried to apply Omar's patchs from this link :&amp;nbsp;&lt;A href="https://community.nxp.com/thread/330749"&gt;IPU2 parallel port on IMX6Q&lt;/A&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;All ios are muxed correctly. Checked with IMX6QDRM datasheet.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;With an oscilloscope there are PIXCLK V/HSYNC and DATA when cat /dev/video0 is clalled.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks for your help&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 11 Oct 2018 13:11:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6q-IPU2-CSI1-timeout/m-p/847499#M129752</guid>
      <dc:creator>Rbe78</dc:creator>
      <dc:date>2018-10-11T13:11:55Z</dc:date>
    </item>
    <item>
      <title>Re: imx6q IPU2 CSI1 timeout</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6q-IPU2-CSI1-timeout/m-p/847500#M129753</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I patched the adv7180_tvin driver to works with adv7183.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Now i have an image but it is very dark. I think it is a problem with AGC.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I work on it&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 12 Oct 2018 06:53:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6q-IPU2-CSI1-timeout/m-p/847500#M129753</guid>
      <dc:creator>Rbe78</dc:creator>
      <dc:date>2018-10-12T06:53:30Z</dc:date>
    </item>
    <item>
      <title>Re: imx6q IPU2 CSI1 timeout</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6q-IPU2-CSI1-timeout/m-p/847501#M129754</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;It works.&lt;/P&gt;&lt;P&gt;It was an electric problem.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Solved !&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 12 Oct 2018 19:22:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6q-IPU2-CSI1-timeout/m-p/847501#M129754</guid>
      <dc:creator>Rbe78</dc:creator>
      <dc:date>2018-10-12T19:22:00Z</dc:date>
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