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    <title>i.MX ProcessorsのトピックCSI and Mipi</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/CSI-and-Mipi/m-p/846596#M129642</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;in another thread,&lt;/P&gt;&lt;P&gt;"&lt;/P&gt;&lt;P&gt;For iMX6DQ, there are two IPUs, so they can support up to 4 cameras at the same time. But the default BSP can only support up to two cameras at the same time.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="untitled.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/66220iFB10AE944357F7AE/image-size/large?v=v2&amp;amp;px=999" role="button" title="untitled.png" alt="untitled.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;The attached patch can make the BSP support up to 4 cameras based on 3.10.53 GA 1.1.0 BSP.&lt;/P&gt;&lt;P style="min- padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The 4 cameras can be:&lt;/P&gt;&lt;P&gt;- 1xCSI, 3xMIPI&lt;/P&gt;&lt;P&gt;- 2xCSI, 2xMIPI&lt;/P&gt;&lt;P&gt;- 4xMIPI&lt;/P&gt;&lt;P style="min- padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;For 4xMIPI case, the four cameras should be combined on the single MIPI CSI2 interface, and each camera data should be transfered on a mipi virtual channel.&lt;/P&gt;&lt;P&gt;"&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Question, can you help to give explain to "1xCSI, 3xMIPI"? How about "3xCSI, 1xMIPI"?Why 4xMIPI four cameras shoule be combined on the single MIPI CSI2 interface?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 24 Jul 2018 08:37:30 GMT</pubDate>
    <dc:creator>jiujinhong</dc:creator>
    <dc:date>2018-07-24T08:37:30Z</dc:date>
    <item>
      <title>CSI and Mipi</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/CSI-and-Mipi/m-p/846596#M129642</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;in another thread,&lt;/P&gt;&lt;P&gt;"&lt;/P&gt;&lt;P&gt;For iMX6DQ, there are two IPUs, so they can support up to 4 cameras at the same time. But the default BSP can only support up to two cameras at the same time.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="untitled.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/66220iFB10AE944357F7AE/image-size/large?v=v2&amp;amp;px=999" role="button" title="untitled.png" alt="untitled.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;The attached patch can make the BSP support up to 4 cameras based on 3.10.53 GA 1.1.0 BSP.&lt;/P&gt;&lt;P style="min- padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The 4 cameras can be:&lt;/P&gt;&lt;P&gt;- 1xCSI, 3xMIPI&lt;/P&gt;&lt;P&gt;- 2xCSI, 2xMIPI&lt;/P&gt;&lt;P&gt;- 4xMIPI&lt;/P&gt;&lt;P style="min- padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;For 4xMIPI case, the four cameras should be combined on the single MIPI CSI2 interface, and each camera data should be transfered on a mipi virtual channel.&lt;/P&gt;&lt;P&gt;"&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Question, can you help to give explain to "1xCSI, 3xMIPI"? How about "3xCSI, 1xMIPI"?Why 4xMIPI four cameras shoule be combined on the single MIPI CSI2 interface?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 24 Jul 2018 08:37:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/CSI-and-Mipi/m-p/846596#M129642</guid>
      <dc:creator>jiujinhong</dc:creator>
      <dc:date>2018-07-24T08:37:30Z</dc:date>
    </item>
    <item>
      <title>Re: CSI and Mipi</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/CSI-and-Mipi/m-p/846597#M129643</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;refer to the figure, imx6 just has two CSI ports, so the max CSI number is two, and mx6 has 4 virtual channels for mipi, should be connected max 4 mipi, so you can know the reason couldn't connect 3CSI+1MIPI, because mx6 just has one mipi/csi2 port, so 4 mipi need to combined on the single MIPI CSI2 interface&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 26 Jul 2018 07:40:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/CSI-and-Mipi/m-p/846597#M129643</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2018-07-26T07:40:06Z</dc:date>
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