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    <title>topic Re: If iMX8M with DDR3L design,the platform need to patch bl31.bin? in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/If-iMX8M-with-DDR3L-design-the-platform-need-to-patch-bl31-bin/m-p/845349#M129526</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Generally the Arm trusted firmware BL31 should not depend on memory type.&lt;/P&gt;&lt;P&gt;The patch is intended for&amp;nbsp;&lt;SPAN style="color: #000000; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial; display: inline !important; float: none;"&gt;DVFS and will work only with same type memories as our EVK.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; Look at the following:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/473927"&gt;imx8mq GA release: DDR initialization in ATF&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 25 Jul 2018 03:34:32 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2018-07-25T03:34:32Z</dc:date>
    <item>
      <title>If iMX8M with DDR3L design,the platform need to patch bl31.bin?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/If-iMX8M-with-DDR3L-design-the-platform-need-to-patch-bl31-bin/m-p/845348#M129525</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi All&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The community had release for LPDDR4 bl31.bin patch, if customer use DDR3L design platform, the platform need to patch bl31.bin or not?&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-340179"&gt;https://community.nxp.com/docs/DOC-340179&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 24 Jul 2018 08:28:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/If-iMX8M-with-DDR3L-design-the-platform-need-to-patch-bl31-bin/m-p/845348#M129525</guid>
      <dc:creator>felixhsu</dc:creator>
      <dc:date>2018-07-24T08:28:14Z</dc:date>
    </item>
    <item>
      <title>Re: If iMX8M with DDR3L design,the platform need to patch bl31.bin?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/If-iMX8M-with-DDR3L-design-the-platform-need-to-patch-bl31-bin/m-p/845349#M129526</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Generally the Arm trusted firmware BL31 should not depend on memory type.&lt;/P&gt;&lt;P&gt;The patch is intended for&amp;nbsp;&lt;SPAN style="color: #000000; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial; display: inline !important; float: none;"&gt;DVFS and will work only with same type memories as our EVK.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; Look at the following:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/473927"&gt;imx8mq GA release: DDR initialization in ATF&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Jul 2018 03:34:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/If-iMX8M-with-DDR3L-design-the-platform-need-to-patch-bl31-bin/m-p/845349#M129526</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2018-07-25T03:34:32Z</dc:date>
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