topic Re: i.MX 6UltraLite too slow results in CoreMark in i.MX Processors

i.MX 6UltraLite too slow results in CoreMark

moiaraya — Thu, 15 Nov 2018 14:21:23 GMT

I would like to test the bare-metal performance of the i.MX 6UltraLite processor. For that I ran the CoreMark by using the MCIMX6UL-EVK2 Evaluation Board and got some -too slow- results compared to other similar processors, as follows:

2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 1633459
Total time (secs): 163.345900
Iterations/Sec : 61.219780
Iterations : 10000
Compiler version : IAR ARM 8.32
Compiler flags : High Speed - No Size Contraints
Memory location : STACK
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0x988c
Correct operation validated. See readme.txt for run and reporting rules.
CoreMark 1.0 : 61.219780 / IAR ARM 8.32 High Speed - No Size Contraints / STACK

I just wanted to ask whether I'm missing something or this is the expected performance for the Cortex-A7 @ 528MHz + NEON?

I attach my core_portme.c file to make sure the initialization is correct.

Thanks!

Moises

Re: i.MX 6UltraLite too slow results in CoreMark

igorpadykov — Fri, 16 Nov 2018 03:22:41 GMT

Hi Jose

coremark figures obtained for i.MX6UL EVK L3.14.38_6UL_GA release may be obatined

with creating service request: How to submit a new question for NXP Support

Regarding coremark source code optimization - this can be supported only using

extended support with NXP Professional Services:

NXP Professional Services|NXP

Best regards
igor
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Re: i.MX 6UltraLite too slow results in CoreMark

moiaraya — Fri, 16 Nov 2018 15:37:24 GMT

Hi Igor,

Thanks for helping. Unfortunately, creating a service request is not an option for me at the moment . Moreover, beyond than just getting some results I wanted to tell how to optimize the MX6UL performance in a bare-metal environment to compare it to a Linux environment. From this post I think it can be that I still need to activate L1 and L2 cache of the processor.

Could you point me out how to enable both cache in the initialization for this processor in a bare-metal enviroment? I'm using the IAR ARM 8.32 compiler for this test.

Regarding the source code optimization for the CoreMark benchmark: I would actually want to avoid that the benchmark can be optimized, either by modifying it by hand or letting the compiler optimize it. As I'll be using 2 different compilers to run my tests (probably GCC and ARM) I wouldn't like to measure how well those 2 compilers can optimize the code but what is the overhead of one target environment over the other running on the same processor + RAM. I found this in the CoreMark site:

"Unlike Dhrystone, CoreMark has specific run and reporting rules, and was designed to avoid problematic aspects of Dhrystone. For example, major portions of Dhrystone actually expose the compiler’s ability to optimize the workload rather than the capabilities of an MCU or CPU. Dhrystone is thus more revealing as a compiler benchmark than as a hardware benchmark."

Thanks again!

Jose