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    <title>topic imx6sl uart rts/cts in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx6sl-uart-rts-cts/m-p/840533#M128939</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hi ,&lt;/P&gt;&lt;P&gt;&amp;nbsp;my chip is imx6sl, I use uart4 with rts and cts ,&lt;/P&gt;&lt;P&gt;the set is as follow. but&amp;nbsp; the imx6sl's rts pin (&lt;SPAN&gt;MX6SL_PAD_SD1_DAT6__UART4_RTS_B) is always high.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;whether should I pull it down force or my set is something&amp;nbsp; wrong.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;pinctrl_uart4_1: uart4grp-1 {&lt;BR /&gt; fsl,pins = &amp;lt;&lt;BR /&gt; MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x1b0b1&lt;BR /&gt; MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x1b0b1&lt;BR /&gt; MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x1b0b1&lt;BR /&gt; MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x1b0b1&lt;BR /&gt; &amp;gt;;&lt;BR /&gt; };&lt;/P&gt;&lt;P&gt;&amp;amp;uart4 {&lt;BR /&gt; pinctrl-names = "default";&lt;BR /&gt; pinctrl-0 = &amp;lt;&amp;amp;pinctrl_uart4_1&amp;gt;;&lt;BR /&gt; fsl,uart-has-rtscts;&lt;BR /&gt; status = "okay";&lt;BR /&gt; /* for DTE mode, add below change */&lt;BR /&gt; /* fsl,dte-mode; */&lt;BR /&gt; /* pinctrl-0 = &amp;lt;&amp;amp;pinctrl_uart4dte_1&amp;gt;; */&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&amp;amp;usdhc1 {&lt;BR /&gt; status = "disabled";&lt;BR /&gt;};&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 23 Jul 2018 09:44:45 GMT</pubDate>
    <dc:creator>yan2anfei</dc:creator>
    <dc:date>2018-07-23T09:44:45Z</dc:date>
    <item>
      <title>imx6sl uart rts/cts</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6sl-uart-rts-cts/m-p/840533#M128939</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hi ,&lt;/P&gt;&lt;P&gt;&amp;nbsp;my chip is imx6sl, I use uart4 with rts and cts ,&lt;/P&gt;&lt;P&gt;the set is as follow. but&amp;nbsp; the imx6sl's rts pin (&lt;SPAN&gt;MX6SL_PAD_SD1_DAT6__UART4_RTS_B) is always high.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;whether should I pull it down force or my set is something&amp;nbsp; wrong.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;pinctrl_uart4_1: uart4grp-1 {&lt;BR /&gt; fsl,pins = &amp;lt;&lt;BR /&gt; MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x1b0b1&lt;BR /&gt; MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x1b0b1&lt;BR /&gt; MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x1b0b1&lt;BR /&gt; MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x1b0b1&lt;BR /&gt; &amp;gt;;&lt;BR /&gt; };&lt;/P&gt;&lt;P&gt;&amp;amp;uart4 {&lt;BR /&gt; pinctrl-names = "default";&lt;BR /&gt; pinctrl-0 = &amp;lt;&amp;amp;pinctrl_uart4_1&amp;gt;;&lt;BR /&gt; fsl,uart-has-rtscts;&lt;BR /&gt; status = "okay";&lt;BR /&gt; /* for DTE mode, add below change */&lt;BR /&gt; /* fsl,dte-mode; */&lt;BR /&gt; /* pinctrl-0 = &amp;lt;&amp;amp;pinctrl_uart4dte_1&amp;gt;; */&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&amp;amp;usdhc1 {&lt;BR /&gt; status = "disabled";&lt;BR /&gt;};&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 23 Jul 2018 09:44:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6sl-uart-rts-cts/m-p/840533#M128939</guid>
      <dc:creator>yan2anfei</dc:creator>
      <dc:date>2018-07-23T09:44:45Z</dc:date>
    </item>
    <item>
      <title>Re: imx6sl uart rts/cts</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6sl-uart-rts-cts/m-p/840534#M128940</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi yan2&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;UART_RTS&amp;nbsp; direction is output in DTE mode according to&lt;/P&gt;&lt;P&gt;Table 55. UART I/O Configuration vs. Mode i.MX6SL Datasheet &lt;BR /&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fwww.nxp.com%2Fdocs%2Fen%2Fdata-sheet%2FIMX6SLCEC.pdf" rel="nofollow" target="_blank"&gt;https://www.nxp.com/docs/en/data-sheet/IMX6SLCEC.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;so one can try to uncomment dte statement in dts file and check&lt;/P&gt;&lt;P&gt;bit DCEDTE in UARTx_UFCR register.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 23 Jul 2018 10:47:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6sl-uart-rts-cts/m-p/840534#M128940</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-07-23T10:47:00Z</dc:date>
    </item>
    <item>
      <title>Re: imx6sl uart rts/cts</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6sl-uart-rts-cts/m-p/840535#M128941</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;thank you very much.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 23 Jul 2018 13:46:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6sl-uart-rts-cts/m-p/840535#M128941</guid>
      <dc:creator>yan2anfei</dc:creator>
      <dc:date>2018-07-23T13:46:42Z</dc:date>
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