i.mx28 default Exception addresses

RamanJamloki — Thu, 16 Feb 2012 06:42:06 GMT

Hi All, I am looking for the default exception addresses for i.mx28 processor. I beleive they must be in somewhere in OCRAM or OCROM. The only thing I found in i.mx28 manual is below

The following exceptions are recognized by the core:
• SWI—Software interrupt
• UNDEF—Undefined instruction
• PABT—Instruction prefetch abort
• FIQ—Fast peripheral interrupt
• IRQ—Normal peripheral interrupt
• DABT—Data abort
• RESET—Reset
• BKPT—Breakpoint
The vector table pointing to these interrupts can be located at physical address 0x00000000
or 0xFFFF0000. The i.MX28 maps its 64-Kbyte on-chip ROM to the address 0xFFFF0000
to 0xFFFFFFFF. The core is hardwired to use the high address vector table at hard reset
(core port VINITHI =1).

In the memory map chapter the on chip ROM address starts form C0000000 and the size is 128K. Thatis confusing.

I want to give pointer of own exception handlers at the default exception addresses. Any information on this regard would be of great help.

Thanks

Raman

Re: i.mx28 default Exception addresses

Yuri — Thu, 16 Feb 2012 07:44:12 GMT

The address 0xffff0018 is located in internal ROM area and, therefore
cannot be changed. But ROM code provides all activities to support the Interrupt
Collector (ICOLL) of the i.MX28. So, just configure ICOLL for proper operation. Please
take a look at Chapter 5 [Interrupt Collector] of the i.MX28 Reference Manual.

Another approach is to use the ARM core MMU to remap IRQ vector 0xffff0018 to
SDRAM address range.

Also, it is possible to change the CP15:C1:V to 0 in order to force exceptions to low address
vector configuration. In such case OCRAM may be used.

topic Re: i.mx28 default Exception addresses in i.MX Processors

i.mx28 default Exception addresses

Re: i.mx28 default Exception addresses