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    <title>topic Re: Documentation for iMX8M CSI? in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Documentation-for-iMX8M-CSI/m-p/836113#M128357</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The reference manual covers only the configuration of the MIPI phy, but not of the CSI controller.&amp;nbsp; E.g. the registers at 0x30a9000 are not described in the reference manual.&amp;nbsp; Chapter 13.6 references a "CSI-2 Controller User Giuce" but I do not know where to find this document.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 31 Aug 2018 13:33:22 GMT</pubDate>
    <dc:creator>ensc</dc:creator>
    <dc:date>2018-08-31T13:33:22Z</dc:date>
    <item>
      <title>Documentation for iMX8M CSI?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Documentation-for-iMX8M-CSI/m-p/836111#M128355</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;where can I find the documentation about the iMX8 CSI controller?&amp;nbsp;&amp;nbsp; IMX8MDQLQRM rev.0 ("i.MX 8M Dual/8M QuadLite/8M Quad&lt;BR /&gt;Applications Processors Reference Manual") does not describe this subsystem.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Accordingly Linux kernel sources, it seems to be compatible with i.MX6SX CSI, but driver uses bits which are undocumented and marked as "reserved" in the iMX6SX Reference Manual (IMX6SXRM rev. 3); e.g. driver contains&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;PRE class="language-c line-numbers"&gt;&lt;CODE&gt;&lt;SPAN class="comment token"&gt;/* csi control reg 18 */&lt;/SPAN&gt;
&lt;SPAN class="property macro token"&gt;#define BIT_CSI_ENABLE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (0x1 &amp;lt;&amp;lt; 31)&lt;/SPAN&gt;
&lt;SPAN class="property macro token"&gt;#define BIT_MIPI_DATA_FORMAT_RAW8&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (0x2a &amp;lt;&amp;lt; 25)&lt;/SPAN&gt;
&lt;SPAN class="property macro token"&gt;#define BIT_MIPI_DATA_FORMAT_RAW10&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (0x2b &amp;lt;&amp;lt; 25)&lt;/SPAN&gt;
&lt;SPAN class="property macro token"&gt;#define BIT_MIPI_DATA_FORMAT_YUV422_8B&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (0x1e &amp;lt;&amp;lt; 25)&lt;/SPAN&gt;
&lt;SPAN class="property macro token"&gt;#define BIT_MIPI_DATA_FORMAT_MASK&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (0x3F &amp;lt;&amp;lt; 25)&lt;/SPAN&gt;
&lt;SPAN class="property macro token"&gt;#define BIT_MIPI_DATA_FORMAT_OFFSET&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 25&lt;/SPAN&gt;
‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍&lt;SPAN class="line-numbers-rows"&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/CODE&gt;&lt;/PRE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;but manual describes this register as&lt;/P&gt;&lt;P&gt;&lt;SPAN class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;IMG alt="pastedImage_1.png" src="https://community.nxp.com/t5/image/serverpage/image-id/67711i7FE7E5665256181F/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_1.png" /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In iMX8 manuals, it is completely missing.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 02 Nov 2020 14:14:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Documentation-for-iMX8M-CSI/m-p/836111#M128355</guid>
      <dc:creator>ensc</dc:creator>
      <dc:date>2020-11-02T14:14:23Z</dc:date>
    </item>
    <item>
      <title>Re: Documentation for iMX8M CSI?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Documentation-for-iMX8M-CSI/m-p/836112#M128356</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;For camera input, there is MIPI-CSI (4-lanes each) only.&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-8-processors/i.mx-8m-family-armcortex-a53-cortex-m4-audio-voice-video:i.MX8M" title="https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-8-processors/i.mx-8m-family-armcortex-a53-cortex-m4-audio-voice-video:i.MX8M"&gt;i.MX 8M Applications Processor | Arm® Cortex®-A53, Cortex-M4 | 4K display resolution |NXP&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For details, please read chapter 13.6 in Reference manual.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Aug 2018 03:11:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Documentation-for-iMX8M-CSI/m-p/836112#M128356</guid>
      <dc:creator>jimmychan</dc:creator>
      <dc:date>2018-08-30T03:11:24Z</dc:date>
    </item>
    <item>
      <title>Re: Documentation for iMX8M CSI?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Documentation-for-iMX8M-CSI/m-p/836113#M128357</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The reference manual covers only the configuration of the MIPI phy, but not of the CSI controller.&amp;nbsp; E.g. the registers at 0x30a9000 are not described in the reference manual.&amp;nbsp; Chapter 13.6 references a "CSI-2 Controller User Giuce" but I do not know where to find this document.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 31 Aug 2018 13:33:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Documentation-for-iMX8M-CSI/m-p/836113#M128357</guid>
      <dc:creator>ensc</dc:creator>
      <dc:date>2018-08-31T13:33:22Z</dc:date>
    </item>
    <item>
      <title>Re: Documentation for iMX8M CSI?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Documentation-for-iMX8M-CSI/m-p/836114#M128358</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;i have the same problem. at the moment. i think the file mx6s_capture.c is written for imx7. in the datasheet of the imx7 i found the documentation of all registers from mx6s_capture.c&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;(CSI_CSICR1) (CSI_CSICR2) (CSI_CSICR3) (CSI_CSISTATFIFO) (CSI_CSIRXCNT) .... (CSI_CSICR18)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;it could be that the csi of the IMX7 and IMX8 is the same?!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 05 Nov 2018 16:21:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Documentation-for-iMX8M-CSI/m-p/836114#M128358</guid>
      <dc:creator>joachimjaehn</dc:creator>
      <dc:date>2018-11-05T16:21:48Z</dc:date>
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