<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: What should be the tCL value for this DDR3 memory ? in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/What-should-be-the-tCL-value-for-this-DDR3-memory/m-p/832579#M127869</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Hello,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;The parameter tCL of the i.MX6 Reference Manual really is CAS Latency, defined as the&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;delay, in clock cycles, between the internal Read command and the availability of the first&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;bit of output data. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency (CL); &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;RL = AL + CL.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; The CAS latency is programmable value. It may be recommended to leave its value without changing, &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;as in the (Excel) tool suggested. Note, tCL may depend on DDR frequency and the same value must be &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;used in i.MX6 MMDC and DRAM part (in Mode Register MR0). &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; From DRAM Datasheet, Table 2 (Speed Grade Information), recommended CL is 11 clocks for 800 MHz &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;memory device, meaning 13.75 ns; for 400 MHz, 13.75 ns is 6 clocks. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; In the (Excel) table, 7 is taken for assurance.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Have a great day,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Yuri&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Note: If this post answers your question, please click the Correct Answer &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;button. Thank you!&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 29 Aug 2018 06:43:24 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2018-08-29T06:43:24Z</dc:date>
    <item>
      <title>What should be the tCL value for this DDR3 memory ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/What-should-be-the-tCL-value-for-this-DDR3-memory/m-p/832578#M127868</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm referring to the attached ddr init script and could you please help me to fill it correctly ?&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;My memory is&amp;nbsp; AS4C256M16D3A-12BCN data sheet attached here with.&amp;nbsp;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Processor i.MX6Q&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;1) What should be the tCL value for this memory ? I can't find it in data sheet.&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/67680i3F0A884FED7DF891/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;2) Can you please check this script and tell me whether it is correct or not for my memory module ?&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Peter.&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 28 Aug 2018 14:32:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/What-should-be-the-tCL-value-for-this-DDR3-memory/m-p/832578#M127868</guid>
      <dc:creator>peteramond</dc:creator>
      <dc:date>2018-08-28T14:32:13Z</dc:date>
    </item>
    <item>
      <title>Re: What should be the tCL value for this DDR3 memory ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/What-should-be-the-tCL-value-for-this-DDR3-memory/m-p/832579#M127869</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Hello,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;The parameter tCL of the i.MX6 Reference Manual really is CAS Latency, defined as the&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;delay, in clock cycles, between the internal Read command and the availability of the first&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;bit of output data. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency (CL); &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;RL = AL + CL.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &amp;nbsp; The CAS latency is programmable value. It may be recommended to leave its value without changing, &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;as in the (Excel) tool suggested. Note, tCL may depend on DDR frequency and the same value must be &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;used in i.MX6 MMDC and DRAM part (in Mode Register MR0). &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; From DRAM Datasheet, Table 2 (Speed Grade Information), recommended CL is 11 clocks for 800 MHz &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;memory device, meaning 13.75 ns; for 400 MHz, 13.75 ns is 6 clocks. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; In the (Excel) table, 7 is taken for assurance.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Have a great day,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Yuri&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Note: If this post answers your question, please click the Correct Answer &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;button. Thank you!&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Aug 2018 06:43:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/What-should-be-the-tCL-value-for-this-DDR3-memory/m-p/832579#M127869</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2018-08-29T06:43:24Z</dc:date>
    </item>
    <item>
      <title>Re: What should be the tCL value for this DDR3 memory ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/What-should-be-the-tCL-value-for-this-DDR3-memory/m-p/832580#M127870</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/Yuri"&gt;Yuri&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you very much for your feedback.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Then what should be the tCWL value for the Excel table ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/67606iE364F670E4ABC90C/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is that same as tCL ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Could you please help me on this ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Peter.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Aug 2018 07:12:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/What-should-be-the-tCL-value-for-this-DDR3-memory/m-p/832580#M127870</guid>
      <dc:creator>peteramond</dc:creator>
      <dc:date>2018-08-29T07:12:26Z</dc:date>
    </item>
    <item>
      <title>Re: What should be the tCL value for this DDR3 memory ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/What-should-be-the-tCL-value-for-this-DDR3-memory/m-p/832581#M127871</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp;Generally it is possible to have different CAS latencies for read and write operations.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Good practice is to leave this parameter as the Excel table recommends.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~Yuri.&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Aug 2018 07:47:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/What-should-be-the-tCL-value-for-this-DDR3-memory/m-p/832581#M127871</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2018-08-29T07:47:12Z</dc:date>
    </item>
    <item>
      <title>Re: What should be the tCL value for this DDR3 memory ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/What-should-be-the-tCL-value-for-this-DDR3-memory/m-p/832582#M127872</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/Yuri"&gt;Yuri&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you. But it is saying obtain this value from ddr data sheet. I cant see tCWL value in data sheet.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is that okay to leave it as 6 ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Peter.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Aug 2018 08:21:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/What-should-be-the-tCL-value-for-this-DDR3-memory/m-p/832582#M127872</guid>
      <dc:creator>peteramond</dc:creator>
      <dc:date>2018-08-29T08:21:28Z</dc:date>
    </item>
    <item>
      <title>Re: What should be the tCL value for this DDR3 memory ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/What-should-be-the-tCL-value-for-this-DDR3-memory/m-p/832583#M127873</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp; The memory Datasheet states about 11 clocks for 800 MHz.&lt;/P&gt;&lt;P&gt;Therefore&amp;nbsp; the values of the tool are quire reasonable for specific (400 MHz)&lt;/P&gt;&lt;P&gt;configuration.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Aug 2018 09:21:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/What-should-be-the-tCL-value-for-this-DDR3-memory/m-p/832583#M127873</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2018-08-29T09:21:56Z</dc:date>
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  </channel>
</rss>

