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    <title>i.MX ProcessorsのトピックeMMC Normal boot not work with x4,x8 DDR setting.</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/eMMC-Normal-boot-not-work-with-x4-x8-DDR-setting/m-p/832283#M127830</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello community,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I tested eMMC(rev 5.01) boot with i.mx6q sabre-sd USDHC2 I/F.&lt;/P&gt;&lt;P&gt;In fast boot mode (BOOT_CFG1[4] = 1), it can boot from boot partition both x8 and x4 DDR mode.&lt;/P&gt;&lt;P&gt;In normal boot mode (&lt;SPAN&gt;BOOT_CFG1[4] = 0) with x1,x4,x8 SDR mode, it can boot correctly.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;But normal&amp;nbsp;boot mode (&lt;SPAN&gt;BOOT_CFG1[4] = 0) with x4,x8 SDR mode, it can not boot both user partition and&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;boot partition of eMMC.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;Base setting of USDHC boot eFUSE descriptions as following.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 60px;"&gt;&lt;SPAN&gt;&lt;SPAN&gt;&lt;BR /&gt;BOOT_CFG1[7:6] : 01 - boot from USDHC&lt;BR /&gt;BOOT_CFG1[5] : 1 - eMMC&lt;BR /&gt;BOOT_CFG1[4] : 0 - Normal boot&lt;BR /&gt;BOOT_CFG1[3:2] : 00 - High speed mode&lt;BR /&gt;BOOT_CFG1[1] : 0 - eMMC reset disable&lt;BR /&gt;BOOT_CFG1[0] : 0 - Throught the SD pad&lt;BR /&gt;BOOT_CFG2[7:5] : 101 - 4bit DDR&lt;BR /&gt;BOOT_CFG2[4:3] : 01 - USDHC-2&lt;BR /&gt;BOOT_CFG2[2] : 0 - Boot ROM default&lt;BR /&gt;BOOT_CFG2[1] : 0 - Boot acknowledge enable&lt;BR /&gt;BOOT_CFG2[0] : 0 - Use default values&lt;BR /&gt;MMC_DLL_DLY[6:0] : 0000000&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 60px;"&gt;&lt;SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;Of case, I try to change&amp;nbsp;BOOT_BUS_CONDITIONS [177] and&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;PARTITION_CONFIG (before BOOT_CONFIG) [179] in eMMC.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;To boot eMMC with x4,x8 DDR in normal boot, need some more setting?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;To see the eMMC bus signal log on ROM boot function,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;I.MX6 output MMC_CMD and parameter based on the device boot flow in the IMX6DQRM Figure 8-11 and 8-16.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;Switch command (CMD6) set&amp;nbsp;PARTITION_CONFIG(0x01B34900), Hi-speed(0x03B9_0100) and BUS_WIDTH(0x03B70500) and eMMC respond with no error.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;After send READ_MULTIPLE_BLOCK(CMD18) and read 512byte from sector 0,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;i.MX6 stop MMC_CLK and no response any more.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;Best regards,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;Ishii.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 04 Dec 2018 11:26:24 GMT</pubDate>
    <dc:creator>takayuki_ishii</dc:creator>
    <dc:date>2018-12-04T11:26:24Z</dc:date>
    <item>
      <title>eMMC Normal boot not work with x4,x8 DDR setting.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/eMMC-Normal-boot-not-work-with-x4-x8-DDR-setting/m-p/832283#M127830</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello community,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I tested eMMC(rev 5.01) boot with i.mx6q sabre-sd USDHC2 I/F.&lt;/P&gt;&lt;P&gt;In fast boot mode (BOOT_CFG1[4] = 1), it can boot from boot partition both x8 and x4 DDR mode.&lt;/P&gt;&lt;P&gt;In normal boot mode (&lt;SPAN&gt;BOOT_CFG1[4] = 0) with x1,x4,x8 SDR mode, it can boot correctly.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;But normal&amp;nbsp;boot mode (&lt;SPAN&gt;BOOT_CFG1[4] = 0) with x4,x8 SDR mode, it can not boot both user partition and&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;boot partition of eMMC.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;Base setting of USDHC boot eFUSE descriptions as following.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 60px;"&gt;&lt;SPAN&gt;&lt;SPAN&gt;&lt;BR /&gt;BOOT_CFG1[7:6] : 01 - boot from USDHC&lt;BR /&gt;BOOT_CFG1[5] : 1 - eMMC&lt;BR /&gt;BOOT_CFG1[4] : 0 - Normal boot&lt;BR /&gt;BOOT_CFG1[3:2] : 00 - High speed mode&lt;BR /&gt;BOOT_CFG1[1] : 0 - eMMC reset disable&lt;BR /&gt;BOOT_CFG1[0] : 0 - Throught the SD pad&lt;BR /&gt;BOOT_CFG2[7:5] : 101 - 4bit DDR&lt;BR /&gt;BOOT_CFG2[4:3] : 01 - USDHC-2&lt;BR /&gt;BOOT_CFG2[2] : 0 - Boot ROM default&lt;BR /&gt;BOOT_CFG2[1] : 0 - Boot acknowledge enable&lt;BR /&gt;BOOT_CFG2[0] : 0 - Use default values&lt;BR /&gt;MMC_DLL_DLY[6:0] : 0000000&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 60px;"&gt;&lt;SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;Of case, I try to change&amp;nbsp;BOOT_BUS_CONDITIONS [177] and&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;PARTITION_CONFIG (before BOOT_CONFIG) [179] in eMMC.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;To boot eMMC with x4,x8 DDR in normal boot, need some more setting?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;To see the eMMC bus signal log on ROM boot function,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;I.MX6 output MMC_CMD and parameter based on the device boot flow in the IMX6DQRM Figure 8-11 and 8-16.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;Switch command (CMD6) set&amp;nbsp;PARTITION_CONFIG(0x01B34900), Hi-speed(0x03B9_0100) and BUS_WIDTH(0x03B70500) and eMMC respond with no error.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;After send READ_MULTIPLE_BLOCK(CMD18) and read 512byte from sector 0,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;i.MX6 stop MMC_CLK and no response any more.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;Best regards,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN&gt;Ishii.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 04 Dec 2018 11:26:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/eMMC-Normal-boot-not-work-with-x4-x8-DDR-setting/m-p/832283#M127830</guid>
      <dc:creator>takayuki_ishii</dc:creator>
      <dc:date>2018-12-04T11:26:24Z</dc:date>
    </item>
    <item>
      <title>Re: eMMC Normal boot not work with x4,x8 DDR setting.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/eMMC-Normal-boot-not-work-with-x4-x8-DDR-setting/m-p/832284#M127831</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A _jive_internal="true" data-content-finding="Community" data-userid="301689" data-username="takayuki_ishii" href="https://community.nxp.com/people/takayuki_ishii"&gt;Takayuki&lt;/A&gt;,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; I compared your configurations for booting with Lists in Reference Manual, and your settings is no problem.SD2 signals are connected to SD connector, I couldn't confirm if SD / eMMC card inserted supports eMMC DDR mode.&lt;/P&gt;&lt;P&gt;So my suggestion is :&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; On i.MX6Q SabreSDP board, eMMC is supported, and it is connected to SD4 port, you can test it.&amp;nbsp; See below , please!&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/67016i93389E092709DEA9/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;(1) Populate R712 to Board.&lt;/P&gt;&lt;P&gt;(2) Setting Pin 4 &amp;amp; Pin3 on SW6 to be 10 for x8 or 01 for x4 mode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a nice day!&lt;/P&gt;&lt;P&gt;NXP TIC weidong sun&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Dec 2018 03:14:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/eMMC-Normal-boot-not-work-with-x4-x8-DDR-setting/m-p/832284#M127831</guid>
      <dc:creator>weidong_sun</dc:creator>
      <dc:date>2018-12-11T03:14:50Z</dc:date>
    </item>
    <item>
      <title>Re: eMMC Normal boot not work with x4,x8 DDR setting.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/eMMC-Normal-boot-not-work-with-x4-x8-DDR-setting/m-p/832285#M127832</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Sun,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for your reply and sorry my less information.&lt;/P&gt;&lt;P&gt;I already shorted R712.&lt;/P&gt;&lt;P&gt;So both SD2(eMMC with SD-card socket adapter) and SDD4(on board eMMC) work&lt;/P&gt;&lt;P&gt;with DDR boot setting with EXT_CSD on eMMC device.&lt;/P&gt;&lt;P&gt;&amp;nbsp; BOOT_BUS_CONDITIONS [177].BOOT_MODE=0x02&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Do I need some more setting to use DDR finction?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards.&lt;/P&gt;&lt;P&gt;Ishii.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 14 Dec 2018 01:00:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/eMMC-Normal-boot-not-work-with-x4-x8-DDR-setting/m-p/832285#M127832</guid>
      <dc:creator>takayuki_ishii</dc:creator>
      <dc:date>2018-12-14T01:00:03Z</dc:date>
    </item>
    <item>
      <title>Re: eMMC Normal boot not work with x4,x8 DDR setting.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/eMMC-Normal-boot-not-work-with-x4-x8-DDR-setting/m-p/1441439#M189101</link>
      <description>&lt;P&gt;I am on i.mx8mm and have similar problem.&lt;/P&gt;&lt;P&gt;We have used Micron eMMC in 8-bit DDR BOOT_CFG for a long time without problem. We now replace eMMC with corresponding Kioxia eMMC and ROM do not boot. Memory works perfect in U-boot and Linux when we bootstrap via serial download.&lt;/P&gt;&lt;P&gt;No plausible ideas what was problem from Kioxia/NXP as it should work. Then by almost an accident we changed to SDR mode and then it started working.&lt;BR /&gt;&lt;BR /&gt;Did you ever get any insight in your problems Ishii?&lt;/P&gt;</description>
      <pubDate>Fri, 08 Apr 2022 16:52:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/eMMC-Normal-boot-not-work-with-x4-x8-DDR-setting/m-p/1441439#M189101</guid>
      <dc:creator>petter-osterlund</dc:creator>
      <dc:date>2022-04-08T16:52:43Z</dc:date>
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