topic Re: DDR4 CK_A and CK_B Functionality in i.MX Processors

DDR4 CK_A and CK_B Functionality

alistair_schofi — Tue, 04 Dec 2018 08:11:04 GMT

Hi,

I'm currently designing a module using the i.MX8MQ and I am in the middle of creating a schematic using 4 Micron DDR4 x8 memory chips. I'm slightly apprehensive about the usage of CK_T/C_A and CK_T/C_B. I was just wondering how these clocks should be connected to the 4 independent DDR4 chips? I (quite possibly naively) think that CK_A should run to bytes 0 and 1 of the DDR4 and that CK_B should run to bytes 2 and 3 because the LPDDR4 used on the reference design sort of implies that is the case. Can someone confirm this is correct for me? I've also tried to find something more explicit in the hardware design guide but have been unable to do so.

Thanks for any help in advance.

Re: DDR4 CK_A and CK_B Functionality

Yuri — Wed, 05 Dec 2018 08:42:48 GMT

Hello,

CK_T/C_A are intended for CS0 and CK_T/C_B - for CS1.

Have a great day,

Yuri

------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer

button. Thank you!

Re: DDR4 CK_A and CK_B Functionality

alistair_schofi — Wed, 05 Dec 2018 12:06:39 GMT

Thanks for the help Yuri, I appreciate it.

If I could be cheeky and ask a quick follow up question...

Am I right in presuming that if I am using 4 DDR4 x8 memory chips then the first 2 devices/bytes would receive this CK_T/C_A, CS0, CKE0 and ODT0? And conversely the second 2 device/bytes would receive CK_T/C_A, CS0, CKE0 and ODT0?

Thanks again for your help in advance.

Re: DDR4 CK_A and CK_B Functionality

Yuri — Thu, 06 Dec 2018 05:13:01 GMT

Hello,

Yes, You configuration is correct, assuming 32-bit data port at CS0.

Regards,

Yuri.