Clarification on TZ WDOG

johnbaczewski — Mon, 17 Sep 2018 21:20:41 GMT

Clarification/ Understand of TZ WDOG.

I’m designing a custom i.MX6UL design – From what I understand there are 3 external Watchdog signals (WDOG1-3_B which are either inputs or outputs). The Security Ref. Manual states that “TZ WDOG is another instantiation of the system WDOG.” (which is WDOG2).

QUESTION 1: Does this mean there are only 2 Internal Watchdog Timers but they could be mapped to either of the 3 external watchdog signals?

The following shows the operational states from Security Ref. Manual (Section 1.3)

If not serviced, the TZ WDOG security violation alarm goes to the SNVS.

Not certain if these States match the wording from the standard Reference Manual regarding TZ Wdog as follows:

The first Red Arrow indicates that wdog_rst_b is "Activated" but the second arrow indicates that it is Activated by software.

Question 2-4: Please clarify how wdog_rst_b is Activated (is software involved?)?

Can TZ Wdog only be mapped to external WDOG2_b?

Am I guaranteed that Reset (both internal and external reset) will happen due to TZ WDOG expiration and that it cannot be circumvented?

I found this diagram under Post 653405, but I don’t see anything similar under i.MX6UL.

Question 5: Is this a valid dwg. for the i.MX6UL?

Thanks

John Bacz...

Re: Clarification on TZ WDOG

Yuri — Thu, 20 Sep 2018 07:27:42 GMT

Hello,

Please look at my comments below.

IMX 6UL supports three watchdog timers (WDOG1/2/3).

Table 57-1 (WDOG External Signals) of i.MX 6UltraLite Reference Manual (RM),

Rev. 1, 04/2016, shows three separate sets of watchdog signals. Because of

pin multiplexing it is possible to select different pins for each of the three

watchdogs. But, say, TZ WDOG cab be mapped only to its external WDOG2 pin.

Watchdog (time-out) events may be causes both either (hardware) timer one

or software, clearing bit SRS (Software Reset Signal) in WDOGx_WCR register.

Use section 57.6 (Initialization) of the RM how to use the WDOGs.

but the TZ WDOG(2) cannot be masked. Also, the TZ WDOG module cannot be programmed

or deactivated by a normal mode SW.

Let me remind the Watch Dog Timer supports two comparison points

during each counting period. Each of the comparison points is configurable to evoke

an interrupt to the ARM core, and a second point evokes an external event on

the WDOG line.

The figure, showing i.MX6 WDOG is applied to i.MX 6UL in general, take into account

three WDOGs of i.MX 6UL.

Have a great day,

Yuri

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topic Re: Clarification on TZ WDOG in i.MX Processors

Clarification on TZ WDOG

Re: Clarification on TZ WDOG