topic Re: imx7 ADC Predevider in i.MX Processors

imx7 ADC Predevider

erikfriedel — Mon, 27 Aug 2018 13:18:52 GMT

This question may seems trivial, but I just can't find an answer.

In the i.MX7 Dual Applications Processor Reference Manual, "IMX7DRM.pdf" at page 4941 you can see 14.1.4: Clocks and timing.

The Global clock the ADC is receiving is 24MHz. The Manual says, that the adc analogue clock can vary from 300kHz to 6MHz and that the 24MHz clock can be devided by 4, 8, 16, 32, 64 and 128.

My problem is, that 24MHz : 128 = 187.5kHz. How does this work, and why did the manual say 300kHz?

Could someone please explain it to me?

Best regards

Re: imx7 ADC Predevider

Yuri — Tue, 28 Aug 2018 07:32:35 GMT

Hello,

According to hardware specs of the i.MX7, shown in i.MX7 Datasheet(s)

in table, named “Recommended operating conditions for 12-bit ADC”

parameter Main Clock Frequency FCLK should be in range 300 KHz - 6 MHz.

Have a great day,

Yuri

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Re: imx7 ADC Predevider

erikfriedel — Tue, 28 Aug 2018 10:20:32 GMT

Thank you

My question is, why you are able to select the 128 divider. This would result in a analogue core clock of 187500Hz, wouldn't it?

Re: imx7 ADC Predevider

Yuri — Tue, 28 Aug 2018 10:30:01 GMT

Hello,

the 128 divider is a feature, supported by generic IP, embedded in i.MX.

Regards,

Yuri.