topic Re: i.MX7D 2BG DDR calibration in i.MX Processors

i.MX7D 2BG DDR calibration

oferausterlitz — Sun, 26 Aug 2018 11:37:59 GMT

Hi,

I am attempting to calibrate an i.MX7D with 2GB RAM consisting of 2x 8gb DDR RAM chips of Samsung

P/N: K4B8G1646D-MYK0. The chip internal configuration is a dual die configuration with CS0 and CS1.

1. I am using the "MX7D_DDR3_register_programming_aid_v1_2" spread sheet with following parameters:

Memory type:	DDR3
Manufacturer:	Samsung
Memory part number:	K4B8G1646D-MYK0
Density of each DRAM device (Gb):	8
Number of DRAM devices per chip select	2
Density per chip select (Gb)¹:	8
Number of Chip Selects used²	2
Total DRAM density (Gb)	16
Number of ROW Addresses²	15
Number of COLUMN Addresses²	10
Number of BANK addresses²	3
Number of BANKS²	8
Bus Width: 32 or 16 (bits)	32
Clock Cycle Freq (MHz)³	533
Clock Cycle Time (ns)	1.876

Note: the number of ROW addresses in the chip pinout table is 15. I assume this is since it is a dual die chip in which each die is 4gb

2. I am using v2.80 DDR Test Tool.

DDR Density is set to 1GB since setting to 2GB prints an error:

"Error, selected density is higher than what is supported!
Modify and Re-download again!!!"

Setting to 1GB i can see the following print:

===========================================

DDR configuration
DDR type is DDR3
Data width: 32, bank num: 8
Row size: 15, col size: 10
Two chip selects are used
Density per chip select: 1024MB
Total density is 2048MB
============================================

3. I then run calibration at 528Mhz.

Read calibration starts but then fails with the error: Error: failed during ddr calibration

Are DRAMs with 2 Chip selects configuration supported by the i.MX7D and the test tool?

Are there any errors in the above settings?

Thanks for your help.

Re: i.MX7D 2BG DDR calibration

igorpadykov — Sun, 26 Aug 2018 23:40:57 GMT

Hi Ofer

one can try latest v.2.9 tool

i.MX6/7 DDR Stress Test Tool V2.90

density selection for i.MX7D is described in FAQ section on that thread.

Calibration errors may be caused by layout errors (by the way, what about other

memory tests, do they pass), please check layout rules in

Hardware Development Guide for i.MX7Dual and 7Solo Applications Processors
http://www.nxp.com/files/32bit/doc/user_guide/IMX7DSHDG.pdf

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

Re: i.MX7D 2BG DDR calibration

oferausterlitz — Tue, 28 Aug 2018 07:29:02 GMT

Hi,

Further checking this, I have done rework to the MCIMX7SABRE board replacing the DDR ICs to K4B8G1646D-MYK0 mentioned above and installed the ZQ termination resistors for CS1 R81,R82.

I am using the above definitions in the spreadsheet v1.2 which is the latest and trying to calibrate the DDR using latest DDR tool V2.90.

The calibration is unstable. It does not pass at 528Mhz. At 400Mhz and even at 350Mhz it will sometimes pass and sometimes fail in the middle with the error I mentioned above. One thing I noticed is that when changing in the spreadsheet the default setting of "ROW-BANK Interleaving" field from "Enabled" to "Disabled" and using the .ds file produced with same parameters, the calibration succeeds.

My question is therefore if you have any information whether using a 2 CS configuration for 2GB supported and in what mode?

Thanks Again.

Re: i.MX7D 2BG DDR calibration

igorpadykov — Tue, 28 Aug 2018 08:00:21 GMT

not sure that I fully understood your question, probably below thread answers it

https://community.nxp.com/message/601517

what about other memory tests, do they pass.

For passing calibration one can try to tweak drive strength settings.

~igor

Re: i.MX7D 2BG DDR calibration

oferausterlitz — Tue, 28 Aug 2018 11:40:38 GMT

Hi,

Each of my memory chips are connected to both CS0 & CS1

I have tested with DDR CS field set to: '0' as suggested in DDR tool FAQ and also tested with field set to 'ALL'.

The post you mentioned refers to setting the filed to '1', i.e. performing calibration only for CS1.

What registers need to be 'tweaked'?

Are DDR ICs with Dual Die configuration using both chip selects same as I am testing been validated by NXP?

Is the desired mode of operation in i.MX7D ROW-BANK Interleaving?

Aviad

Re: i.MX7D 2BG DDR calibration

igorpadykov — Tue, 28 Aug 2018 12:07:39 GMT

drive strength can be changed in MX7D_DDR3_register_programming_aid_v1_2.xlsx
i.MX7D DRAM Register Programming Aid

address/cmd drive strength setting : sect.9.3.4.21 DDR_PHY_DRVDS_CON0
data drive strength setting : sect.9.3.4.24 DDR_PHY_ZQ_CON0 i.MX7D Reference Manual
http://cache.nxp.com/files/32bit/doc/ref_manual/IMX7DRM.pdf

For ddr memory, its drive strength can be changed using register MR1 during initialization.

also may be useful to look on

i.MX7D with 2GB of DDR3 memory

~igor