Parallel video to CSI at 60 frames per second, IPU tasks

darin111 — Mon, 17 Dec 2012 18:40:01 GMT

I am trying to get a 60 fps SVGA parallel video signal in IPU1 CSI0. The hardware is getting the signals fine, but currently my driver is architected to wait for the SMFC EOF interrupt, then do some things to initiate the IDMAC transfer. For reference, I am in Windows Embedded Compact 7, using the i.MX53 WEC7 camera driver as a base for my driver.

I would like to use the IPU tasks so that the CPU and driver are not part of that acquisition chain. The reference manual mentions IPU tasks as a way of doing that, but there is no detail on how to configure these tasks. Has anyone used an IPU task to automate the CSI->SMFC->IDMAC process? If so, any help on how to configure and use such IPU tasks would be greatly appreciated.

Thanks

Re: Parallel video to CSI at 60 frames per second, IPU tasks

justin_jiang — Wed, 27 Mar 2013 02:21:12 GMT

Yes our IPU can support the automatic flow controlled by FSU.

Please refer to the following registers:

IPU_FS_PROC_FLOW1

IPU_FS_PROC_FLOW2

IPU_FS_PROC_FLOW3

IPU_FS_DISP_FLOW1

IPU_FS_DISP_FLOW2

You must set the source and destination of a sub-module to chain them.

Taking the use case CSI->SMFC->IDMAC->MEM->DP FG for display as an example:

IPU_IPU_FS_PROC_FLOW3__SMFC0_DEST_SEL = 0xA // destination to channel 27

IPU_IPU_FS_DISP_FLOW1__DP_SYNC1_SRC_SEL = 0x1 // DP FG source from SMFC0

Then the capture->display would be linked and triggered automatically.

i.MX Processors中的主题 Parallel video to CSI at 60 frames per second, IPU tasks

Parallel video to CSI at 60 frames per second, IPU tasks

Re: Parallel video to CSI at 60 frames per second, IPU tasks