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    <title>i.MX ProcessorsのトピックRe: Long gaps between SPI transmissions</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Long-gaps-between-SPI-transmissions/m-p/818345#M126080</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi marcingrzelak&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;gaps may be caused by delays intoduced by bus arbiters NIC-301 and&lt;/P&gt;&lt;P&gt;I am afraid there is no way to avoid it. If possible one can try to use bursts&lt;/P&gt;&lt;P&gt;configured by ECSPIx_CONREG register.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 23 Oct 2018 00:19:01 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2018-10-23T00:19:01Z</dc:date>
    <item>
      <title>Long gaps between SPI transmissions</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Long-gaps-between-SPI-transmissions/m-p/818344#M126079</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;in my program&amp;nbsp;I would like to read an external time counter by SPI and&amp;nbsp;I would like to receive a fairly accurate time. But when I starts transmissions&amp;nbsp;one after another,&amp;nbsp; the difference between successive readings is ~70&amp;nbsp;us. A few us for SPI transmissions and remaining time is the gap between transmissions.&amp;nbsp;How can I minimize this gap?&amp;nbsp;&lt;/P&gt;&lt;P&gt;I'm using SPI by ioctl.&lt;/P&gt;&lt;P&gt;Thanks for help.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 22 Oct 2018 18:50:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Long-gaps-between-SPI-transmissions/m-p/818344#M126079</guid>
      <dc:creator>marcingrzelak</dc:creator>
      <dc:date>2018-10-22T18:50:42Z</dc:date>
    </item>
    <item>
      <title>Re: Long gaps between SPI transmissions</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Long-gaps-between-SPI-transmissions/m-p/818345#M126080</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi marcingrzelak&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;gaps may be caused by delays intoduced by bus arbiters NIC-301 and&lt;/P&gt;&lt;P&gt;I am afraid there is no way to avoid it. If possible one can try to use bursts&lt;/P&gt;&lt;P&gt;configured by ECSPIx_CONREG register.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 23 Oct 2018 00:19:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Long-gaps-between-SPI-transmissions/m-p/818345#M126080</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-10-23T00:19:01Z</dc:date>
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