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    <title>topic Re: IMX6ULL - CSI NTSC Interlaced Capture in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816376#M125755</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello rickman,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; See below, please!&lt;/P&gt;&lt;P&gt;------------------&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/67791i81811A7C86037C9C/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;--------------------------------------------------------------&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If you don't have files in attachments, you can&amp;nbsp; submit a case to me via our salesforce system, I will send them to you by email!&lt;/P&gt;&lt;P&gt;You can follow below steps to submit your case:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1. open the link&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fwww.nxp.com%2Fsupport%2Fsupport%3ASUPPORTHOME" rel="nofollow" target="_blank"&gt;https://www.nxp.com/support/support:SUPPORTHOME&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2.In the middle of web page, under "Support Requests"，Press "Go to Tickets"。&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;3.Log in；or register a new account，log in personal emal to validate information。&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;4.Log in web via account，Press "Add a folder"&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;5.after success, Add a new case? to submit a new question&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;weidong sun&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 28 Aug 2018 01:43:02 GMT</pubDate>
    <dc:creator>weidong_sun</dc:creator>
    <dc:date>2018-08-28T01:43:02Z</dc:date>
    <item>
      <title>IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816374#M125753</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We have NTSC video decoder giving BT656 input, we have verified the decoder is outputting correct,&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Following IMX6UL TRM,&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/473846"&gt;i.mx6ul CSI receive interlace ccir656 video issue &lt;/A&gt;&amp;nbsp; and&amp;nbsp;&lt;A href="https://community.nxp.com/thread/480516"&gt;iMX7D : NTSC Video Capture&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;both doesn't answer the conclusion how&amp;nbsp;&lt;/P&gt;&lt;P&gt;We tried as per the &lt;A _jive_internal="true" href="https://community.nxp.com/thread/473846"&gt;https://community.nxp.com/thread/473846&lt;/A&gt; we even used the patch which was supplied by NXP, however their input was PAL, not NTSC.&lt;/P&gt;&lt;P&gt;Question we have&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;How to configure Deinterlace stride should it be (720*2/8) ?&lt;/LI&gt;&lt;LI&gt;How De-interlace stride and FBUF_STRIDE related. We saw CMA size is having effect in the DMA operations.&lt;/LI&gt;&lt;LI&gt;We want to capture BT656 NTSC 525/60 signal with deinterlaced enabled.&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;Is there any programming guide we can follow?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Answer from &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/dh29"&gt;dh29&lt;/A&gt;‌ about this forum, we tried, then we get some output but its garbled.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you in advance,&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 22 Aug 2018 22:34:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816374#M125753</guid>
      <dc:creator>rick_man</dc:creator>
      <dc:date>2018-08-22T22:34:59Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816375#M125754</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/dh29"&gt;dh29&lt;/A&gt;‌ &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/igorshakirov"&gt;igorshakirov&lt;/A&gt;‌ any comments?&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Aug 2018 23:04:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816375#M125754</guid>
      <dc:creator>rick_man</dc:creator>
      <dc:date>2018-08-27T23:04:22Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816376#M125755</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello rickman,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; See below, please!&lt;/P&gt;&lt;P&gt;------------------&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/67791i81811A7C86037C9C/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;--------------------------------------------------------------&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If you don't have files in attachments, you can&amp;nbsp; submit a case to me via our salesforce system, I will send them to you by email!&lt;/P&gt;&lt;P&gt;You can follow below steps to submit your case:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1. open the link&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fwww.nxp.com%2Fsupport%2Fsupport%3ASUPPORTHOME" rel="nofollow" target="_blank"&gt;https://www.nxp.com/support/support:SUPPORTHOME&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2.In the middle of web page, under "Support Requests"，Press "Go to Tickets"。&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;3.Log in；or register a new account，log in personal emal to validate information。&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;4.Log in web via account，Press "Add a folder"&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;5.after success, Add a new case? to submit a new question&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;weidong sun&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 28 Aug 2018 01:43:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816376#M125755</guid>
      <dc:creator>weidong_sun</dc:creator>
      <dc:date>2018-08-28T01:43:02Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816377#M125756</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi rickman,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I see that you are using an i.MX6, which has an IPU, where I am using an i.MX7 without an IPU. As such the Linux framework used to process the CSI-MIPI is completely different.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I've finally got the i.MX7 working for both PAL and NTSC using the ADV7280 in PROGRESSIVE mode. See my post&amp;nbsp;&lt;A href="https://community.nxp.com/thread/480516"&gt;https://community.nxp.com/thread/480516&lt;/A&gt;&amp;nbsp;which I have just updated with how I got NTSC finally working. Unfortunately I don't think this will help your problem!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 28 Aug 2018 09:16:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816377#M125756</guid>
      <dc:creator>dh29</dc:creator>
      <dc:date>2018-08-28T09:16:50Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816378#M125757</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/dh29"&gt;dh29&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;No i am using IMX6ULL, and I followed your recent NTSC update hardcodinig the NTSC resolution instead of 480, and now I see some problem, but mostly due to my wrong configuration.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I think you and I are both in same page and same domain, yours is IMX7D and our platform is IMX6UL.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;-Rick&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 28 Aug 2018 19:05:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816378#M125757</guid>
      <dc:creator>rick_man</dc:creator>
      <dc:date>2018-08-28T19:05:16Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816379#M125758</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/weidong.sun"&gt;weidong.sun&lt;/A&gt;‌,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We really appreciate your response, but we want answer on below.&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; font-size: 14px;"&gt;Question we have&lt;/P&gt;&lt;OL style="color: #51626f; background-color: #ffffff; border: 0px; font-size: 14px; padding: 0px 0px 0px 30px;"&gt;&lt;LI style="border: 0px; font-weight: inherit; font-size: 14px; margin: 0.5ex 0px;"&gt;How to configure Deinterlace stride should it be (720*2/8) ?&lt;/LI&gt;&lt;LI style="border: 0px; font-weight: inherit; font-size: 14px; margin: 0.5ex 0px;"&gt;How De-interlace stride and FBUF_STRIDE related. We saw CMA size is having effect in the DMA operations.&lt;/LI&gt;&lt;LI style="border: 0px; font-weight: inherit; font-size: 14px; margin: 0.5ex 0px;"&gt;We want to capture BT656 NTSC 525/60 signal with deinterlaced enabled.&lt;/LI&gt;&lt;LI style="border: 0px; font-weight: inherit; font-size: 14px; margin: 0.5ex 0px;"&gt;Why when we set FBUF_STRIDE to zero it works? Is there any calculation we need to do?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;It would be really helpful if we have some example, with NTSC and PAL both BT656 input, taken as example and walk through the desired configuration with de-interlacer enabled.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&amp;nbsp;&lt;/P&gt;&lt;P&gt;-Rick&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 28 Aug 2018 19:24:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816379#M125758</guid>
      <dc:creator>rick_man</dc:creator>
      <dc:date>2018-08-28T19:24:16Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816380#M125759</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Rick,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Ah, I didn't realize that the i.MX6ULL also doesn't have an IPU. I'm afraid I only have experience of the i.MX7.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For the i.MX7 I used the Linux 'sub-device' framework i.e. /drivers/media/platform/mxc/subdev. I had to write a driver for the ADV7280, which I based on 'ov5647_mipi.c' and 'ov5640_mipi.c'. I also patched file 'mx6s_capture.c':&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;For NTSC, I hard-coded the image size within function csi_set_imagpara() to 720x507. Its 507 because my Composite-Video to MIPI chip (ADV7280) is configured as a PROGRESSIVE output. I'm not sure what you would need for INTERLACED as you would get heights of 253 &amp;amp; 254.&lt;/LI&gt;&lt;LI&gt;I had to add a definition for YUYV-16 (format used by the ADV7280) in 'struct mx6s_fmt'&lt;/LI&gt;&lt;LI&gt;I also had to set both FBUF_STRIDE and DEINTERLACE_STRIDE to &lt;STRONG&gt;zero&lt;/STRONG&gt;&amp;nbsp;i.e. Register CSI_CSIFBUF_PARA = 0x00. [This contradicts the i.MX7 manual, which I find very poorly written with regard to the CSI MIPI sections.]&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I then also ignored the i.MX V4L2 test applications.[I couldn't get them to work properly, and as I'm not building using YOCTO (I'm using BuildRoot) I kept having to jump back to a YOCTO build-system to re-compile the test-apps.] Instead I used &lt;STRONG&gt;gstreamer-1.0&lt;/STRONG&gt; for testing. The following was used to capture 3 frames to a file:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;gst-launch-1.0 v4l2src device=/dev/video1 num-buffers=3 ! 'video/x-raw,format=(string)UYVY,width=(int)720,height=(int)507' ! filesink location=./tmp1&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;One of the problems I found of getting support on this forum regarding Video-Capture is that you can get 'answers' that are very specific to a particular Linux build / i.MX / capture-Device, which can be very misleading for your own platform. [I include my own answers here!] Hopefully something might help trigger a solution for you.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Aug 2018 08:48:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816380#M125759</guid>
      <dc:creator>dh29</dc:creator>
      <dc:date>2018-08-29T08:48:53Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816381#M125760</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;HI Rick,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Just to correct my statement:&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;UL&gt;&lt;LI&gt;I had to add a definition for YUYV-16 (format used by the ADV7280) in 'struct mx6s_fmt'&lt;/LI&gt;&lt;/UL&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;I should have said that I added a definition for &lt;STRONG&gt;UYVY8_2X8&lt;/STRONG&gt; in &lt;STRONG&gt;struct mx6s_fmt&lt;/STRONG&gt; as part of module &lt;STRONG&gt;mxc_mipi_csi.c:&lt;/STRONG&gt;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;static const struct csis_pix_format mipi_csis_formats[] = {&lt;BR /&gt; {&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;.code = MEDIA_BUS_FMT_YUYV8_2X8,&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;.fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;.data_alignment = 16,&lt;BR /&gt; },&lt;BR /&gt; {&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;.code = MEDIA_BUS_FMT_VYUY8_2X8,&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;.fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;.data_alignment = 16,&lt;BR /&gt; },&lt;BR /&gt; &lt;STRONG&gt;{&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;.code = MEDIA_BUS_FMT_UYVY8_2X8,&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;.fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;.data_alignment = 16,&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; },&lt;/STRONG&gt;&lt;BR /&gt; {&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;.code = MEDIA_BUS_FMT_SBGGR8_1X8,&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;.data_alignment = 8,&lt;BR /&gt; }&lt;BR /&gt;};&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Aug 2018 11:12:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816381#M125760</guid>
      <dc:creator>dh29</dc:creator>
      <dc:date>2018-08-29T11:12:58Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816382#M125761</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi richman,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; Below is reply form i.MX Expert team:&lt;/P&gt;&lt;P&gt;-------------------------------------------------------&lt;/P&gt;&lt;P&gt;ou can reference to followed patch, the CSI module and driver&amp;nbsp;are same for iMX6ULL and IMX6UL, and PAL is more easy than NTSC to support:&amp;nbsp; &lt;A _jive_internal="true" class="" data-containerid="1007" data-containertype="700" data-objectid="330092" data-objecttype="102" href="https://community.nxp.com/docs/DOC-330092"&gt;&lt;SPAN style="color: #0066cc; text-decoration: underline;"&gt;&lt;/SPAN&gt;&lt;/A&gt;&lt;A&gt;https://community.nxp.com/docs/DOC-330092&lt;/A&gt;&lt;/P&gt;&lt;P&gt;-------------------------------------------------------&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; Document on the link is what I had sent to you before. this is our internal link, probably you couldn't access it. so I had to copy it and send to you.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; After you patch it to your kernel, you can run images, then you will see all configurations for BT.656.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a nice day!&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;weidong sun&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Aug 2018 03:15:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816382#M125761</guid>
      <dc:creator>weidong_sun</dc:creator>
      <dc:date>2018-08-30T03:15:38Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816383#M125762</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/weidong.sun"&gt;weidong.sun&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Sorry for late reply, the document you linked I am unable to access it. Could you please share the details how can I download it?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;-Rick&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 05 Sep 2018 23:12:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816383#M125762</guid>
      <dc:creator>rick_man</dc:creator>
      <dc:date>2018-09-05T23:12:36Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816384#M125763</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Any update how I can access the content? Should I send email to you??&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 06 Sep 2018 23:48:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816384#M125763</guid>
      <dc:creator>rick_man</dc:creator>
      <dc:date>2018-09-06T23:48:03Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816385#M125764</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/weidong.sun"&gt;weidong.sun&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am unable to access the document, it says unauthorized. How to access this document?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;-Harshesh&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Sep 2018 17:52:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816385#M125764</guid>
      <dc:creator>rick_man</dc:creator>
      <dc:date>2018-09-11T17:52:11Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816386#M125765</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/weidong.sun"&gt;weidong.sun&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please provide me access to this document, we are having lots of delay due to this lack of information and our production is delayed due to this.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please provide a way to move forward,&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;-Rick&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 13 Sep 2018 17:21:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816386#M125765</guid>
      <dc:creator>rick_man</dc:creator>
      <dc:date>2018-09-13T17:21:30Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816387#M125766</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Rick,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Did you receive those documents ? I remember you sent an email to me, asking for them, and I replied you.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a nice day!&lt;/P&gt;&lt;P&gt;NXP TIC weidong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 26 Oct 2018 01:59:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816387#M125766</guid>
      <dc:creator>weidong_sun</dc:creator>
      <dc:date>2018-10-26T01:59:45Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816388#M125767</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Wigro,&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I didn't receive your document. Please provide me access to the document.&amp;nbsp;&lt;/P&gt;&lt;P&gt;-Rick&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 31 Oct 2018 17:17:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816388#M125767</guid>
      <dc:creator>rick_man</dc:creator>
      <dc:date>2018-10-31T17:17:21Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816389#M125768</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hi&amp;nbsp; wigros：&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;我找不到你的这个关于i.mx6ul porting的网页，上面的下载不到，你能分享一下吗，我的邮箱haifeng.jin@cecport.com&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 23 Apr 2019 06:31:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816389#M125768</guid>
      <dc:creator>haifeng_jin</dc:creator>
      <dc:date>2019-04-23T06:31:28Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816390#M125769</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Wigro, &lt;/P&gt;&lt;P&gt;&lt;SPAN class="" lang="en"&gt;&lt;SPAN class="" title=""&gt;Can you provide this patches and other documents for BT656?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" lang="en"&gt;&lt;SPAN class="" title=""&gt;&lt;SPAN title=""&gt;Will it work on linux 4.14?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" lang="en"&gt;&lt;SPAN class="" title=""&gt;&lt;SPAN title=""&gt;-Pavel&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 29 Jul 2019 07:51:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816390#M125769</guid>
      <dc:creator>pavelbats</dc:creator>
      <dc:date>2019-07-29T07:51:17Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816391#M125770</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi wei dong:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;I also need this patch file and documentation, thank you！&amp;nbsp; My email is&amp;nbsp; &amp;nbsp; 542270618@qq.com&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 04 Dec 2019 12:32:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816391#M125770</guid>
      <dc:creator>liyu1</dc:creator>
      <dc:date>2019-12-04T12:32:50Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6ULL - CSI NTSC Interlaced Capture</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816392#M125771</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;This website can't be opened ！&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 04 Dec 2019 12:33:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6ULL-CSI-NTSC-Interlaced-Capture/m-p/816392#M125771</guid>
      <dc:creator>liyu1</dc:creator>
      <dc:date>2019-12-04T12:33:56Z</dc:date>
    </item>
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