<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
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    <title>topic imx6ul efuse boot not working in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815324#M125610</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We have designed and built our own twin IMX6UL application PCBs.&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Using a bare-metal application of ours to deal with all non-volatile programming on this board, we have programmed serial NOR flash memory with a 2nd stage boot loader, main application software(ThreadX based), data sets, etc.&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;All of this works fine when boot is controlled Internal mode by GPIO pin settings on our breadboard PCBs.&amp;nbsp; &amp;nbsp;The iMX6ULs boot as expected, reading from ecSPI4 (CCS0), handing off to 2nd stage boot loader, loading main app and launching... both processors.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Our release PCB design does not have the GPIO pin connects, so we must boot by eFuse.&amp;nbsp; WE have "dress rehearsed" this on our breadboards with discouraging resutls:&amp;nbsp; &amp;nbsp;Of four iMX6UL's that had been booting successfully from GPIO pin override, but then had the eFuse's set:&lt;BR /&gt;&amp;nbsp; &amp;nbsp;1)&amp;nbsp; One of the four iMX6's will boot properly.&amp;nbsp; &amp;nbsp;The software loads in through the ecSPI4 channel just fine.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;2)&amp;nbsp; Three of the four IMX6's fail to boot.&amp;nbsp; Chip select asserts but no communications take place to the NOR flash.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;When we inspect by JTAG the eFUSE configuration for all four processors after power up (by JTAG connect), we see what we programmed (attached):&lt;/P&gt;&lt;P&gt;OCOTP_CFG4:&amp;nbsp; &amp;nbsp; 0x0B000003&amp;nbsp; &amp;nbsp;=&amp;nbsp; BootCFG4 : 0 : BootCFG2 : BootCFG1&amp;nbsp; for using ecSPI4&amp;nbsp;&amp;nbsp;with CCS 0 to Serial ROM&lt;/P&gt;&lt;P&gt;OCOTP_CFG5:&amp;nbsp; &amp;nbsp; 0x00000010&amp;nbsp; &amp;nbsp; =&amp;nbsp; BT_FUSE_SEL&amp;nbsp; (at bit 4)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Note:&amp;nbsp; Don't know if related:&amp;nbsp; &amp;nbsp;On the three that fail to boot in eFUSE,&amp;nbsp; corrupted values of fuses appear in the shadow registers when we do re-load-to-Shadow operations.&amp;nbsp; This is not the case on the one processor that is successfully booting.&amp;nbsp; The corruption often had bit7 of each eFuse byte reporting as "1".&amp;nbsp; &amp;nbsp; However, after power up when the ROM boot loader loads the shadow registers, inspection over JTAG always reports the values we expect (exactly what we believe the fuses should be).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can you confirm we have proper values set the _CFG4 and _CFG5 eFuse words?&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Why is this problem "marginal"...&amp;nbsp; &amp;nbsp;works on one, but not the other three iMX6UL?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Again, before burning these eFuses, all four processors were successfully booting from serial NOR flash using GPIO override.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for any help you can provide&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 08 Nov 2018 16:39:59 GMT</pubDate>
    <dc:creator>dbjohnson</dc:creator>
    <dc:date>2018-11-08T16:39:59Z</dc:date>
    <item>
      <title>imx6ul efuse boot not working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815324#M125610</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We have designed and built our own twin IMX6UL application PCBs.&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Using a bare-metal application of ours to deal with all non-volatile programming on this board, we have programmed serial NOR flash memory with a 2nd stage boot loader, main application software(ThreadX based), data sets, etc.&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;All of this works fine when boot is controlled Internal mode by GPIO pin settings on our breadboard PCBs.&amp;nbsp; &amp;nbsp;The iMX6ULs boot as expected, reading from ecSPI4 (CCS0), handing off to 2nd stage boot loader, loading main app and launching... both processors.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Our release PCB design does not have the GPIO pin connects, so we must boot by eFuse.&amp;nbsp; WE have "dress rehearsed" this on our breadboards with discouraging resutls:&amp;nbsp; &amp;nbsp;Of four iMX6UL's that had been booting successfully from GPIO pin override, but then had the eFuse's set:&lt;BR /&gt;&amp;nbsp; &amp;nbsp;1)&amp;nbsp; One of the four iMX6's will boot properly.&amp;nbsp; &amp;nbsp;The software loads in through the ecSPI4 channel just fine.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;2)&amp;nbsp; Three of the four IMX6's fail to boot.&amp;nbsp; Chip select asserts but no communications take place to the NOR flash.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;When we inspect by JTAG the eFUSE configuration for all four processors after power up (by JTAG connect), we see what we programmed (attached):&lt;/P&gt;&lt;P&gt;OCOTP_CFG4:&amp;nbsp; &amp;nbsp; 0x0B000003&amp;nbsp; &amp;nbsp;=&amp;nbsp; BootCFG4 : 0 : BootCFG2 : BootCFG1&amp;nbsp; for using ecSPI4&amp;nbsp;&amp;nbsp;with CCS 0 to Serial ROM&lt;/P&gt;&lt;P&gt;OCOTP_CFG5:&amp;nbsp; &amp;nbsp; 0x00000010&amp;nbsp; &amp;nbsp; =&amp;nbsp; BT_FUSE_SEL&amp;nbsp; (at bit 4)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Note:&amp;nbsp; Don't know if related:&amp;nbsp; &amp;nbsp;On the three that fail to boot in eFUSE,&amp;nbsp; corrupted values of fuses appear in the shadow registers when we do re-load-to-Shadow operations.&amp;nbsp; This is not the case on the one processor that is successfully booting.&amp;nbsp; The corruption often had bit7 of each eFuse byte reporting as "1".&amp;nbsp; &amp;nbsp; However, after power up when the ROM boot loader loads the shadow registers, inspection over JTAG always reports the values we expect (exactly what we believe the fuses should be).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can you confirm we have proper values set the _CFG4 and _CFG5 eFuse words?&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Why is this problem "marginal"...&amp;nbsp; &amp;nbsp;works on one, but not the other three iMX6UL?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Again, before burning these eFuses, all four processors were successfully booting from serial NOR flash using GPIO override.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for any help you can provide&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 08 Nov 2018 16:39:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815324#M125610</guid>
      <dc:creator>dbjohnson</dc:creator>
      <dc:date>2018-11-08T16:39:59Z</dc:date>
    </item>
    <item>
      <title>Re: imx6ul efuse boot not working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815325#M125611</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi David&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;after boot fail one can attach jtag debugger and check SRC_SBMR1,2 registers for&lt;/P&gt;&lt;P&gt;verifying boot configuration, compare it with good board.&lt;/P&gt;&lt;P&gt;Also recommended to use nxp uboot from &lt;A class="link-titled" href="https://source.codeaurora.org/" title="https://source.codeaurora.org/"&gt;https://source.codeaurora.org/&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;repository:&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://source.codeaurora.org/external/imx/uboot-imx/tree/?h=imx_v2017.03_4.9.88_2.0.0_ga" title="https://source.codeaurora.org/external/imx/uboot-imx/tree/?h=imx_v2017.03_4.9.88_2.0.0_ga"&gt;uboot-imx - i.MX U-Boot&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Nov 2018 02:38:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815325#M125611</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-11-09T02:38:00Z</dc:date>
    </item>
    <item>
      <title>Re: imx6ul efuse boot not working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815326#M125612</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks!&amp;nbsp; &amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;I looked at those SRC regs after realizing that my failing IMX6's had EIM I/O's enabled.&amp;nbsp; The problem&amp;nbsp;&lt;EM&gt;had&lt;/EM&gt; to be unintended boot configuration.&amp;nbsp; That's when I spotted the mistake in BOOT_CFG1, which needs to be &lt;STRONG&gt;0x30&lt;/STRONG&gt;,&amp;nbsp; not &lt;STRONG&gt;0x03&lt;/STRONG&gt;!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So the reported fuse configuration in my first post:&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;OCOTP_CFG4:&amp;nbsp; &amp;nbsp; &lt;STRONG&gt;0x0B000003&lt;/STRONG&gt;&amp;nbsp; &amp;nbsp;=&amp;nbsp; BootCFG4 : 0 : BootCFG2 : BootCFG1&amp;nbsp; for using ecSPI4&amp;nbsp;&amp;nbsp;with CCS 0 to Serial ROM&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;needs to be:&amp;nbsp;&amp;nbsp;&lt;STRONG&gt;0x0B000030&lt;/STRONG&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Lots of eyes here missed that, as perhaps you did too.&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P&gt;And lucky me!&amp;nbsp; &amp;nbsp;I can burn &lt;STRONG&gt;0x0B000033&lt;/STRONG&gt; to&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;OCOTP_CFG4.&amp;nbsp; &amp;nbsp;The lowest 4 bits are "reserved", and to my delight are not factored by the RBL. So I've got all the processors booting ecSPI4/SS0 - Serial NOR from fuses now.&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;I am still puzzled about the erratic variance chip to chip on software commanded read of fuses. Most of IMX6ULs generate bit errors on READ_FUSE_DATA or just re-loading shadows, yet two of my IMX6ULs read fuses correctly on software command.&amp;nbsp; Since the shadows &lt;STRONG&gt;&lt;EM&gt;are&amp;nbsp;&lt;/EM&gt;&lt;/STRONG&gt;accurate after power-on-reset occurs, most users probably can live with that.&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Nov 2018 16:33:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815326#M125612</guid>
      <dc:creator>dbjohnson</dc:creator>
      <dc:date>2018-11-09T16:33:56Z</dc:date>
    </item>
    <item>
      <title>Re: imx6ul efuse boot not working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815327#M125613</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We are now moving ahead to blow eFUSEs in our production PCBs.&amp;nbsp; Up till now, have done this successfully on bread board systems.&amp;nbsp; &amp;nbsp;A totally new problem has emerged in this production lot.&amp;nbsp; &amp;nbsp;We cannot get the right value to burn for BOOTCFG4 on half of our iMX6ULs.&amp;nbsp; &amp;nbsp;(3 of 6 tested so far,&amp;nbsp; &amp;nbsp;fail in identical manner).&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The malfunction:&amp;nbsp; &amp;nbsp;We burn BOOTCFG4 = 0x0B, but find upon reset that BOOTCFG4 is 0x09.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Bit 1 is failing to burn.&amp;nbsp; Full description below.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Could this be component problem??&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;See&amp;nbsp;&lt;span class="lia-inline-image-display-wrapper" image-alt="Capture.PNG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/74233iBD52540C792C356E/image-size/large?v=v2&amp;amp;px=999" role="button" title="Capture.PNG" alt="Capture.PNG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Nov 2018 22:52:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815327#M125613</guid>
      <dc:creator>dbjohnson</dc:creator>
      <dc:date>2018-11-09T22:52:16Z</dc:date>
    </item>
    <item>
      <title>Re: imx6ul efuse boot not working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815328#M125614</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi David&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;Could this be component problem?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;in general yes. Suggest to check board hardware using &lt;BR /&gt;Hardware Development Guide for the i.MX 6UltraLite Applications Processor &lt;BR /&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/www.nxp.com/docs/en/user-guide/IMX6ULHDG.pdf" rel="nofollow" target="_blank"&gt;https://www.nxp.com/docs/en/user-guide/IMX6ULHDG.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;and try chips from other date codes. Contact nxp local marketing office for&lt;/P&gt;&lt;P&gt;FA procedure.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Also suggest to use programming from uboot&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-95458"&gt;https://community.nxp.com/docs/DOC-95458&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Check that during programming no other external devices (like jtag, e.t.c.)&lt;/P&gt;&lt;P&gt;were connected to board. Recommended to check power-up sequence.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 10 Nov 2018 02:53:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815328#M125614</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-11-10T02:53:22Z</dc:date>
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    <item>
      <title>Re: imx6ul efuse boot not working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815329#M125615</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Igor,&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;"c&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;heck that during programming no other external devices (like jtag, e.t.c.)"&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;Are you stating that&amp;nbsp;fuse-burning cannot be done with JTAG deployed firmware?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are experiencing that 25-30% of our iMX's are consistently and repeatably failing to blow one of the 5 configuration fuses (0 --&amp;gt; 1) we set in OCOTP_CFG4.&amp;nbsp; &amp;nbsp;Indeed the utility that I am using to blow fuses is deployed over JTAG.&amp;nbsp; &amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In our production PCB design, our only means to boot the iMX6UL is fuses.&amp;nbsp; I'm not sure there's any choice to get f/w into the processor (that will burn fuses) other than JTAG.&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please confirm that live-JTAG could be the cause of these issues.&lt;/P&gt;&lt;P&gt;&amp;nbsp;Thanks&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 15 Nov 2018 22:27:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815329#M125615</guid>
      <dc:creator>dbjohnson</dc:creator>
      <dc:date>2018-11-15T22:27:51Z</dc:date>
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    <item>
      <title>Re: imx6ul efuse boot not working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815330#M125616</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;David&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;to narrow down issue why " We burn BOOTCFG4 = 0x0B, but find upon reset that BOOTCFG4 is 0x09.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Bit 1 is failing to burn. ", may be suggested to try burning not with jtag but with uboot.&lt;/P&gt;&lt;P&gt;Programming from uboot&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" data-containerid="2004" data-containertype="14" data-objectid="95458" data-objecttype="102" href="https://community.nxp.com/docs/DOC-95458"&gt;Q&amp;amp;A: How to program i.MX6 eFUSE?&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Using jtag please check that power-up sequence was not violated:&lt;/P&gt;&lt;P&gt;not allowed to apply any external signals to unpowered processor until&lt;/P&gt;&lt;P&gt;it fully powers up. From sect.4.2.1 Power-up sequence i.MX6UL Datasheet&lt;BR /&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.nxp.com%2Fdocs%2Fen%2Fdata-sheet%2FIMX6ULCEC.pdf" rel="nofollow" target="_blank"&gt;http://www.nxp.com/docs/en/data-sheet/IMX6ULCEC.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;"NOTE&lt;BR /&gt;Need to ensure that there is no back voltage (leakage) from any supply on&lt;BR /&gt;the board"&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 16 Nov 2018 03:11:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815330#M125616</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-11-16T03:11:17Z</dc:date>
    </item>
    <item>
      <title>Re: imx6ul efuse boot not working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815331#M125617</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #0000ff;"&gt;&lt;STRONG&gt;More about the faulty behavior:&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;My assessment of the problem-&amp;nbsp; &amp;nbsp;when we execute the procedure to burn one or more fuses with our bare-metal burner program running on JTAG,&amp;nbsp; the fuse-read structure used by&amp;nbsp; OCOTP software method is being damaged.&amp;nbsp; This happens on a byte wide basis-- so bytes across all fuse banks will present a common fault on specific bits.&amp;nbsp; Once the fuse reader has this fault,&amp;nbsp; I suspect it fools the burn operation for that bit into behaving as if the fuse is already burned.&amp;nbsp; &amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thankfully, at power on reset of the iMX6UL, a different scheme interprets the fuses, one that accurately captures the true fuse states to the OCOTP shadows and the SRC_SBMRI.&amp;nbsp; So on many IMX's the fuse reads are corrupted, but we indeed did burn the correct fuses and the they will boot from eFUSE&amp;nbsp; (60%)&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #0000ff;"&gt;&lt;STRONG&gt;uboot "out of reach":&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;As our only boot option on this production board is eFUSE, we'd have to have a way to get a uboot app loaded and running free of eFUSE &amp;amp; JTAG.&amp;nbsp; &amp;nbsp;Serial boot the only possibility.. but wasn't provided for in our PCB design.&amp;nbsp; Not to say "impossible", but this would be a tricky hardware effort (aside from the software effort entialed)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #0000ff;"&gt;&lt;STRONG&gt;JTAG&amp;nbsp; may be the problem !&amp;nbsp; &amp;nbsp;&amp;nbsp;Doing JTAG w/o JTAG connection:&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; {&lt;SPAN style="color: #800080;"&gt;&amp;nbsp;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="color: #008000;"&gt;&lt;SPAN style="text-decoration: underline;"&gt;Performed on 6 imx6ul's in a row&lt;/SPAN&gt;.&amp;nbsp; Desired fuses burned.&amp;nbsp; No post-signs of efuse-reader damage }&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;-&amp;nbsp; &amp;nbsp;JTAG in our bare metal efuse-burn firmware&amp;nbsp; (IAR ARMWB) to virgin IMX^UL&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; -&amp;nbsp; &amp;nbsp;Run to immediate break point&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;-&amp;nbsp; &amp;nbsp; Shut down debug session to release the firmware off the break point.&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; -&amp;nbsp; &amp;nbsp;F/W&amp;nbsp; executes a 5 sec delay, more than enough time to disengage a pogo pin JTAG physical connect&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; -&amp;nbsp; &amp;nbsp;F/W then completes task of burning fuse .. with imx free of JTAG interactions.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 16 Nov 2018 16:02:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815331#M125617</guid>
      <dc:creator>dbjohnson</dc:creator>
      <dc:date>2018-11-16T16:02:12Z</dc:date>
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    <item>
      <title>Re: imx6ul efuse boot not working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815332#M125618</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Our problem with fuses on iMX6UL persists.&amp;nbsp; &amp;nbsp;Per my last posting, I was led to believe that if we use a procedure that disconnects JTAG from our circuit board, enters a programmed delay, and then executes the fuse-writing command, we would escape evident &lt;EM&gt;damage to the fuse-reading circuits&lt;/EM&gt; that is resulting from writing fuses.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;With 12 iMX6UL's submitted to this process (JTAG-free fuse burning) we are getting a fall out rate that is comparable with the experience of nearly 30 iMX6ULs that had fuses burned while software ran under active JTAG connection.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The steps we follow to set up boot from fuse configuration:&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;Operation #1:&amp;nbsp; &amp;nbsp;Blow 5 fuse-bits in&amp;nbsp; OCOTP_CFG4 for desired boot configuration&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;Operation #2:&amp;nbsp; &amp;nbsp;Check the 5 fuses are burned after re-powering&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;Operation #3:&amp;nbsp; &amp;nbsp;Command a re-load of OCOTP_ shadows and check them&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;Operation #4:&amp;nbsp; &amp;nbsp;Blow the BOOT_FUSE_SEL (bit 2) of OCOTP_CFG5&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The statistics:&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &lt;STRONG&gt;&amp;nbsp;20%&lt;/STRONG&gt; of iMX's fail Operation #1&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;- Operation #2 reveals this.&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;- Operation #3 informs us that there are fuse misreads at the same bit sites that a fuse failed to burn,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;STRONG&gt;65%&lt;/STRONG&gt;&amp;nbsp; of iMX's reveal issues in Operation #3 , that is fuse misreads (0 --&amp;gt; 1)&amp;nbsp; when re-loading shadows&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;-&amp;nbsp; If the fuse-reader damage does affect one of the 5 bits we burn, (Operation #1 passed) then there is still a chance we can boot the article from its fuses.&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;-&amp;nbsp; In the 20% that fail Operation#1, the fuse reader misreads (byte wise) Bit 1.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;STRONG&gt;? %&lt;/STRONG&gt;&amp;nbsp; iMX's will fail Operation #4 because fuse reader damage affects either&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 1)&amp;nbsp; Bit 4,&amp;nbsp; so that BOOT_FUSE_SEL in OCOTP_CFG5 will not be burnable&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 2)&amp;nbsp; Bit 2&amp;nbsp; &amp;nbsp;so that the LOCK&amp;nbsp; Write-Prevent bit will be misread and disallow furthre fuse writes&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are now at a loss to cite any cause other than iMX6UL defect.&amp;nbsp; &amp;nbsp;Our production runs all have consumed IMX6UL's with same date code.&amp;nbsp; &amp;nbsp;(we don't have other date codes to compare).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This is critical to our product release circuit boards that can only boot from fuse configuration.&amp;nbsp; Please advise&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Dec 2018 13:24:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815332#M125618</guid>
      <dc:creator>dbjohnson</dc:creator>
      <dc:date>2018-12-10T13:24:47Z</dc:date>
    </item>
    <item>
      <title>Re: imx6ul efuse boot not working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815333#M125619</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="Date Code Photo.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/66866i04F2FCC3FCF63F81/image-size/large?v=v2&amp;amp;px=999" role="button" title="Date Code Photo.jpg" alt="Date Code Photo.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Date code being used in all produced circuit boards thus far.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Dec 2018 15:17:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815333#M125619</guid>
      <dc:creator>dbjohnson</dc:creator>
      <dc:date>2018-12-10T15:17:00Z</dc:date>
    </item>
    <item>
      <title>Re: imx6ul efuse boot not working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815334#M125620</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi David&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;so is fuse write/read working fine with procedure described on&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" data-containerid="2004" data-containertype="14" data-objectid="95458" data-objecttype="102" href="https://community.nxp.com/docs/DOC-95458"&gt;Q&amp;amp;A: How to program i.MX6 eFUSE?&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;with official demo image&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/webapp/Download?colCode=L4.9.88_2.0.0_MX6QDLSOLOX&amp;amp;appType=license&amp;amp;location=null" title="https://www.nxp.com/webapp/Download?colCode=L4.9.88_2.0.0_MX6QDLSOLOX&amp;amp;appType=license&amp;amp;location=null"&gt;https://www.nxp.com/webapp/Download?colCode=L4.9.88_2.0.0_MX6QDLSOLOX&amp;amp;appType=license&amp;amp;location=null&lt;/A&gt;&lt;A class="link-titled" href="https://www.nxp.com/webapp/Download?colCode=L4.9.88_2.0.0_MX6UL7D&amp;amp;appType=license&amp;amp;location=null" title="https://www.nxp.com/webapp/Download?colCode=L4.9.88_2.0.0_MX6UL7D&amp;amp;appType=license&amp;amp;location=null"&gt;https://www.nxp.com/webapp/Download?colCode=L4.9.88_2.0.0_MX6UL7D&amp;amp;appType=license&amp;amp;location=null&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;If issue persists only with custom uboot&amp;amp;jtag may be recommended to proceed with&lt;/P&gt;&lt;P&gt;&amp;nbsp;Professional Services for extended support&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/support/support/nxp-professional-services:PROFESSIONAL-SERVICE" title="https://www.nxp.com/support/support/nxp-professional-services:PROFESSIONAL-SERVICE"&gt;NXP Professional Services|NXP&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Dec 2018 00:36:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6ul-efuse-boot-not-working/m-p/815334#M125620</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-12-11T00:36:04Z</dc:date>
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