topic Re: imx7 boot from eMMC in i.MX Processors

imx7 boot from eMMC

cedricjehasse — Tue, 18 Dec 2018 21:57:53 GMT

Hello,

we're trying to boot a custom board with an imx7 and eMMC connected to USDHC3.

The board boots in manufacturing mode, and we're able to write the eMMC from linux loaded by the manufacturing tool.

We've checked the image written to mmcblk2boot0 is correct by reading it with the dd command.

When we reboot the board it's stays in manufacturing mode.

We see the boot ROM sending commands to the eMMC with the 347.22 KHz clock, but never switching to the 20MHz clock.

Is there a way to read boot ROM errors from an imx7? For the imx6 it's been mentioned there's a boot ROM log buffer.

thanks,

Cedric

Re: imx7 boot from eMMC

igorpadykov — Wed, 19 Dec 2018 01:55:52 GMT

Hi Cedric

unfortunately reading ROM errors from an imx7 using boot ROM log buffer

is not documented ("not supported"), in general one can try to recheck boot settings

reading SRC_SBMR1,2 registers with jtag and checking emmc data with logic

analyzer to find where error happens.

Best regards
igor
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Re: imx7 boot from eMMC

cedricjehasse — Wed, 19 Dec 2018 18:18:44 GMT

We got further into our debugging. It looks like the boot ROM is reading from eMMC.

The IVT in OCRAM looks ok, the IVT in DDR is corrupt and u-boot in DDR also looks ok.

We've read this with jtag:

The IVT in OCRAM:

(gdb) x /64xw 0x910400
0x910400: 0x402000d1 0x87800000 0x00000000 0x877ff42c
0x910410: 0x877ff420 0x877ff400 0x00000000 0x00000000
0x910420: 0x877ff000 0x00075000 0x00000000 0x40d401d2
0x910430: 0x048c01cc 0x04003430 0x0500404f 0x88033630
0x910440: 0x00000040 0x84033630 0x00000040 0x00103930
0x910450: 0x02000000 0x00007a30 0x01100401 0xa0017a30
0x910460: 0x03004080 0xa4017a30 0x20001000 0xa8017a30
0x910470: 0x04001080 0x64007a30 0x46004000 0x90047a30
0x910480: 0x01000000 0xd0007a30 0x01003500 0xd4007a30
0x910490: 0x00000100 0xdc007a30 0x04003009 0xe0007a30
0x9104a0: 0x00000804 0xe4007a30 0x06001100 0xf4007a30
0x9104b0: 0x3f030000 0x00017a30 0x09110809 0x04017a30
0x9104c0: 0x0d020700 0x08017a30 0x07040403 0x0c017a30
0x9104d0: 0x06200000 0x10017a30 0x05020204 0x14017a30
0x9104e0: 0x02020303 0x20017a30 0x03080000 0x80017a30
0x9104f0: 0x20008000 0x84017a30 0x00010002 0x90017a30

The IVT in DDR (every word has two bytes set to 0xff)

(gdb) x /64xw 0x877ff400
0x877ff400: 0x40ff00ff 0x87ff00ff 0x00ff00ff 0x87fff4ff
0x877ff410: 0x87fff4ff 0x87fff4ff 0x00ff00ff 0x00ff00ff
0x877ff420: 0x87fff0ff 0x00ff50ff 0x00ff00ff 0x40ff01ff
0x877ff430: 0x04ff01ff 0x04ff34ff 0x05ff40ff 0x88ff36ff
0x877ff440: 0x00ff00ff 0x84ff36ff 0x00ff00ff 0x00ff39ff
0x877ff450: 0x02ff00ff 0x00ff7aff 0x01ff04ff 0xa0ff7aff
0x877ff460: 0x03ff40ff 0xa4ff7aff 0x20ff10ff 0xa8ff7aff
0x877ff470: 0x04ff10ff 0x64ff7aff 0x46ff40ff 0x90ff7aff
0x877ff480: 0x01ff00ff 0xd0ff7aff 0x01ff35ff 0xd4ff7aff
0x877ff490: 0x00ff01ff 0xdcff7aff 0x04ff30ff 0xe0ff7aff
0x877ff4a0: 0x00ff08ff 0xe4ff7aff 0x06ff11ff 0xf4ff7aff
0x877ff4b0: 0x3fff00ff 0x00ff7aff 0x09ff08ff 0x04ff7aff
0x877ff4c0: 0x0dff07ff 0x08ff7aff 0x07ff04ff 0x0cff7aff
0x877ff4d0: 0x06ff00ff 0x10ff7aff 0x05ff02ff 0x14ff7aff
0x877ff4e0: 0x02ff03ff 0x20ff7aff 0x03ff00ff 0x80ff7aff
0x877ff4f0: 0x20ff80ff 0x84ff7aff 0x00ff00ff 0x90ff7aff

U-Boot in DDR:

(gdb) x /64x 0x87800000
0x87800000: 0xea0000b8 0xe59ff014 0xe59ff014 0xe59ff014
0x87800010: 0xe59ff014 0xe59ff014 0xe59ff014 0xe59ff014
0x87800020: 0x87800060 0x878000c0 0x87800120 0x87800180
0x87800030: 0x878001e0 0x87800240 0x878002a0 0xdeadbeef
0x87800040: 0x0badc0de 0xe320f000 0xe320f000 0xe320f000
0x87800050: 0xe320f000 0xe320f000 0xe320f000 0xe320f000
0x87800060: 0xe51fd028 0xe58de000 0xe14fe000 0xe58de004
0x87800070: 0xe3a0d013 0xe169f00d 0xe1a0e00f 0xe1b0f00e
0x87800080: 0xe24dd048 0xe88d1fff 0xe51f2050 0xe892000c
0x87800090: 0xe28d0048 0xe28d5034 0xe1a0100e 0xe885000f
0x878000a0: 0xe1a0000d 0xeb000c00 0xe320f000 0xe320f000
0x878000b0: 0xe320f000 0xe320f000 0xe320f000 0xe320f000
0x878000c0: 0xe51fd088 0xe58de000 0xe14fe000 0xe58de004
0x878000d0: 0xe3a0d013 0xe169f00d 0xe1a0e00f 0xe1b0f00e
0x878000e0: 0xe24dd048 0xe88d1fff 0xe51f20b0 0xe892000c
0x878000f0: 0xe28d0048 0xe28d5034 0xe1a0100e 0xe885000f

Is the IVT in DDR copied over from OCRAM? Or is it read a second time from eMMC?

Have you ever encountered an issue like this?

thanks,

Cedric

Re: imx7 boot from eMMC

igorpadykov — Fri, 21 Dec 2018 03:24:58 GMT

Hi Cedric

so had you run ddr test and updated image with new calibration coefficients

found from test:

i.MX6/7 DDR Stress Test Tool V3.00

Does board boot fine to ddr using other methods, like sd or tftp.

Best regards
igor