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    <title>i.MX ProcessorsのトピックRe: i.mx6ull sd boot bus width</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6ull-sd-boot-bus-width/m-p/811169#M125107</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi David&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;according to sd specification 4 bit bus width operation mode may be selected/deselected&lt;BR /&gt;using ACMD6. The default bus width after power up or GO_IDLE(CMD0) is 1 bit bus width.&lt;/P&gt;&lt;P&gt;For linux usage one can look in sect.32.2.3 Devicetree Binding attached Linux Manual.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sat, 14 Jul 2018 00:21:20 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2018-07-14T00:21:20Z</dc:date>
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      <title>i.mx6ull sd boot bus width</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6ull-sd-boot-bus-width/m-p/811168#M125106</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm mostly following the EVK reference design, but I noticed in the boot config via gpio, the sd card boot setting is hard-wired for 1-bit bus width, yet off-the-shelf sd cards are 4-bit.&amp;nbsp; I read somewhere that during boot you *can* use 1-bit communication (i'm not sure why one would do that) but I don't see anywhere how the sd card peripheral then gets "put back" to 4-bit mode.&amp;nbsp; clearly the EVK works so it's happening somehow, but I'm not seeing where. Is this simply a matter of configuring in the device tree?&amp;nbsp; where and how is the boot sd card changed from 1-bit to 4-bit after boot?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 13 Jul 2018 20:03:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6ull-sd-boot-bus-width/m-p/811168#M125106</guid>
      <dc:creator>dluberger</dc:creator>
      <dc:date>2018-07-13T20:03:15Z</dc:date>
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    <item>
      <title>Re: i.mx6ull sd boot bus width</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6ull-sd-boot-bus-width/m-p/811169#M125107</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi David&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;according to sd specification 4 bit bus width operation mode may be selected/deselected&lt;BR /&gt;using ACMD6. The default bus width after power up or GO_IDLE(CMD0) is 1 bit bus width.&lt;/P&gt;&lt;P&gt;For linux usage one can look in sect.32.2.3 Devicetree Binding attached Linux Manual.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 14 Jul 2018 00:21:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6ull-sd-boot-bus-width/m-p/811169#M125107</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-07-14T00:21:20Z</dc:date>
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