<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: IMX6 AR8031 RGMII signal changes  in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX6-AR8031-RGMII-signal-changes/m-p/810161#M124935</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Zhao&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;one can try to increase drive strength of rgmii signals with IOMUXC_SW_PAD_CTL_PAD_x&lt;/P&gt;&lt;P&gt;registers, so small variations in board voltages (due to processor loading) do not affect&lt;/P&gt;&lt;P&gt;shape of rgmii signals.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sun, 30 Sep 2018 22:58:50 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2018-09-30T22:58:50Z</dc:date>
    <item>
      <title>IMX6 AR8031 RGMII signal changes</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6-AR8031-RGMII-signal-changes/m-p/810160#M124934</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-size: 10.0pt; color: #51626f; background: white;"&gt;On my custom hardware board (design based on sabresd)&lt;/SPAN&gt; ，&lt;SPAN&gt;using PHY as AR8031, 1Gbps rate instability (forced 100M normal), observing RGMII waveform is very bad.&lt;IMG alt="Wave-RGMII-RXD2@1000M" class="image-1 jive-image j-img-original" /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;Signal setup time exceeded 4.3ns in 1Gbps mode, exceeding the design requirements of RGMII.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;IMG alt="Setup-RGMII-RXD2@100M" class="image-2 jive-image j-img-original" /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;But once in the OS system, the accompanying PC network is forced to 1 Gbps, at this time the Gigabit network can work properly (ping 65500), at this time the RGMII setup time is less than 2 ns&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;IMG alt="OK-Setup-RGMII-RXD2@1000M" class="image-3 jive-image j-img-original" /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Question: why does RGMII's signal establishment time change? Is it related to software? I checked IOMUXC_SW_MUX_CTL_PAD_RGMIIxx and did not change before and after entering the system.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Or hardware? Where is it possible?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thank you&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 29 Sep 2018 01:22:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6-AR8031-RGMII-signal-changes/m-p/810160#M124934</guid>
      <dc:creator>zhaotao</dc:creator>
      <dc:date>2018-09-29T01:22:44Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6 AR8031 RGMII signal changes</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6-AR8031-RGMII-signal-changes/m-p/810161#M124935</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Zhao&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;one can try to increase drive strength of rgmii signals with IOMUXC_SW_PAD_CTL_PAD_x&lt;/P&gt;&lt;P&gt;registers, so small variations in board voltages (due to processor loading) do not affect&lt;/P&gt;&lt;P&gt;shape of rgmii signals.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 30 Sep 2018 22:58:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6-AR8031-RGMII-signal-changes/m-p/810161#M124935</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-09-30T22:58:50Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6 AR8031 RGMII signal changes</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6-AR8031-RGMII-signal-changes/m-p/810162#M124936</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi igor,&lt;/P&gt;&lt;P&gt;&amp;nbsp; Thank you for your&amp;nbsp;kind reply.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;First of all, let me add that the RGMII waveform problem I'm talking about is in the UBOOT phase, and it's normal to get into the Linux OS phase.&lt;BR /&gt;&amp;nbsp; &amp;nbsp;However, I read the RGMII related PAD register, and the UBOOT stage and the OS stage are not different.&lt;BR /&gt;From the waveform point of view, the RGMII's RX and TX setup times have been problematic at the same time, so it's not just IMX's PAD drive capability, it's probably board related.&lt;BR /&gt;&amp;nbsp; &amp;nbsp; Any other suggestions is welcome...&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 08 Oct 2018 02:22:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6-AR8031-RGMII-signal-changes/m-p/810162#M124936</guid>
      <dc:creator>zhaotao</dc:creator>
      <dc:date>2018-10-08T02:22:12Z</dc:date>
    </item>
  </channel>
</rss>

