topic Re: IMX7D PCIE Support in i.MX Processors

IMX7D PCIE Support

christsang — Wed, 28 Nov 2018 03:09:30 GMT

Hi everyone,

I am developing on my custom board using imx7. I want to have PCIe NVME SSD support on my board. I have enable several options in my kernel (linux-imx 4.9.11) config.

Here are the options I have added base on the imx7 sabre config and it works on IMX7 Sabre board, in which my NVME SSD can be mounted and transfer data..

CONFIG_PCI=y
CONFIG_PCI_MSI=y
CONFIG_PCI_IMX6=y

CONFIG_BLK_DEV_NVME=y‍‍‍‍‍

For the PCIe part, the connections of PCIE_RST_B and PCIE_DIS_B is different from IMX7D sabre board. The RESET_B is connected to GPIO1_IO13 and the DISABLE_B is connected to GPIO1_IO12 instead.

So I have also modified the device tree as shown below:

&pcie {
     pinctrl-names = "default";
     pinctrl-0 = <&pinctrl_pcie>;
     reset-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
     disable-gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
     status = "okay";
};‍‍‍‍‍‍‍

&iomuxc {
     pinctrl-names = "default";
     pinctrl-0 = <&pinctrl_hog_1>;

     imx7d-sdb {

          pinctrl_hog_1: hoggrp-1 {
               fsl,pins = <
                    MX7D_PAD_EPDC_BDR0__GPIO2_IO28     0x59 /* headphone detect */
               >;
          };
          
          pinctrl_pcie: pciegrp {
               fsl,pins = <
                    MX7D_PAD_GPIO1_IO12__GPIO1_IO12     0x77     /* PCIE_DIS_B */
                    MX7D_PAD_GPIO1_IO13__GPIO1_IO13     0x77     /* PCIE_RST_B */
               >;
          };‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

However my kernel cannot start after this amendment. There should be problems in the pcie node. The kernel can start properly by removal of the entire pcie node as show above, though PCIe feature will be no longer enabled.

Is there anything I did wrong or missed in my approach? Is there any extra configuration on the reset and disable GPIOs?

Please advise.

Chris Tsang

Re: IMX7D PCIE Support

weidong_sun — Thu, 29 Nov 2018 04:04:01 GMT

Hi Charis,

The 2 PINs you are using have been multiplexed to emulate SPI , see imx7d-sdb.dts file:

        pinctrl_spi1: spi1grp {
            fsl,pins = <
                MX7D_PAD_GPIO1_IO09__GPIO1_IO9    0x59
                MX7D_PAD_GPIO1_IO12__GPIO1_IO12    0x59
                MX7D_PAD_GPIO1_IO13__GPIO1_IO13    0x59
            >;

Comment them, please!

Have a nice day!

Best Regards,

NXP TIC Weidong

Re: IMX7D PCIE Support

christsang — Thu, 29 Nov 2018 04:10:47 GMT

Hi Wigros,

Thanks for your reply. In fact I have already removed the spi1 node as I am intended to remove the extended io. That means the above mentioned pin configuration is not exist in my device tree file.

Hence there is no overlapping on the configurations of GPIO1_IO12 and GPIO1_IO13.

Generally, after removing the extended io, all I need to do is just to modify the reset and disable pin corresponding to my board (i.e. GPIO1_IO12 and GPIO1_IO13) right?

Chris

Re: IMX7D PCIE Support

christsang — Thu, 29 Nov 2018 04:21:30 GMT

I had already removed the node from my dts file. There is no other configuration on GPIO1_IO12 and GPIO1_IO13 in my dts file actually.

And here is my patch on the dts file base on the originally imx7d-sdb.dts file.

177,199d176
< 
<      spi4 {
<           compatible = "spi-gpio";
<           pinctrl-names = "default";
<           pinctrl-0 = <&pinctrl_spi1>;
<           status = "okay";
<           gpio-sck = <&gpio1 13 0>;
<           gpio-mosi = <&gpio1 9 0>;
<           cs-gpios = <&gpio1 12 0>;
<           num-chipselects = <1>;
<           #address-cells = <1>;
<           #size-cells = <0>;
< 
<           gpio_spi: gpio_spi@0 {
<                compatible = "fairchild,74hc595";
<                gpio-controller;
<                #gpio-cells = <2>;
<                reg = <0>;
<                registers-number = <1>;
<                registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/
<                spi-max-frequency = <100000>;
<           };
<      };
247,257d223
< &csi1 {
<      csi-mux-mipi = <&gpr 0x14 4>;
<      status = "okay";
< 
<      port {
<           csi_ep: endpoint {
<                remote-endpoint = <&csi_mipi_ep>;
<           };
<      };
< };
< 
275c241
<      pinctrl-assert-gpios = <&gpio_spi 5 GPIO_ACTIVE_HIGH>;
---
>      pinctrl-assert-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
315,339d280
< &mipi_csi {
<      clock-frequency = <240000000>;
<      status = "okay";
<      port {
<           mipi_sensor_ep: endpoint1 {
<                remote-endpoint = <&ov5640_mipi_ep>;
<                data-lanes = <2>;
<                csis-hs-settle = <13>;
<                csis-clk-settle = <2>;
<                csis-wclk;
<           };
< 
<           csi_mipi_ep: endpoint2 {
<                remote-endpoint = <&csi_ep>;
<           };
<      };
< };
< 
< &flexcan2 {
<      pinctrl-names = "default";
<      pinctrl-0 = <&pinctrl_flexcan2>;
<      xceiver-supply = <&reg_can2_3v3>;
<      status = "okay";
< };
< 
345a287,291
>      rtc: isl1208@6f {
>           compatible = "isil,isl1208";
>           reg = <0x6f>;
>      };
> 
560,609d505
< 
<      ov5640_mipi: ov5640_mipi@3c {
<           compatible = "ovti,ov5640_mipi";
<           reg = <0x3c>;
<           clocks = <&clks IMX7D_CLK_DUMMY>;
<           clock-names = "csi_mclk";
<           csi_id = <0>;
<           pwn-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>;
<           AVDD-supply = <&vgen6_reg>;
<           mclk = <24000000>;
<           mclk_source = <0>;
<           port {
<                ov5640_mipi_ep: endpoint {
<                     remote-endpoint = <&mipi_sensor_ep>;
<                };
<           };
<      };
< };
< 
< &lcdif {
<      pinctrl-names = "default";
<      pinctrl-0 = <&pinctrl_lcdif>;
<      enable-gpio = <&gpio_spi 7 GPIO_ACTIVE_LOW>;
<      display = <&display0>;
<      status = "okay";
< 
<      display0: display@0 {
<           bits-per-pixel = <16>;
<           bus-width = <24>;
< 
<           display-timings {
<                native-mode = <&timing0>;
< 
<                timing0: timing0 {
<                     clock-frequency = <9200000>;
<                     hactive = <480>;
<                     vactive = <272>;
<                     hfront-porch = <8>;
<                     hback-porch = <4>;
<                     hsync-len = <41>;
<                     vback-porch = <2>;
<                     vfront-porch = <4>;
<                     vsync-len = <10>;
<                     hsync-active = <0>;
<                     vsync-active = <0>;
<                     de-active = <1>;
<                     pixelclk-active = <0>;
<                };
<           };
<      };
618,620c514,517
<      reset-gpio = <&gpio_spi 1 GPIO_ACTIVE_LOW>;
<      disable-gpio = <&gpio_spi 0 GPIO_ACTIVE_LOW>;
---
>      pinctrl-0 = <&pinctrl_pcie>;
>      reset-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
>      disable-gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
809a707,714
>                     MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13     0x59 /* 100K PU to user button */
>                >;
>           };
> 
>           pinctrl_pcie: pciegrp {
>                fsl,pins = <
>                     MX7D_PAD_GPIO1_IO12__GPIO1_IO12     0x77     /* PCIE_DIS_B */
>                     MX7D_PAD_GPIO1_IO13__GPIO1_IO13     0x77     /* PCIE_RST_B */
908,915d812
<           pinctrl_flexcan2: flexcan2grp {
<                fsl,pins = <
<                     MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX     0x59
<                     MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX     0x59
<                     MX7D_PAD_EPDC_DATA14__GPIO2_IO14      0x59     /* CAN_STBY */
<                >;
<           };
< 
1039,1046d935
<                >;
<           };
< 
<           pinctrl_spi1: spi1grp {
<                fsl,pins = <
<                     MX7D_PAD_GPIO1_IO09__GPIO1_IO9     0x59
<                     MX7D_PAD_GPIO1_IO12__GPIO1_IO12     0x59
<                     MX7D_PAD_GPIO1_IO13__GPIO1_IO13     0x59
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