topic Re: iMX7 external Bus CS1 in i.MX Processors

iMX7 external Bus CS1

mahaep — Tue, 21 Aug 2018 08:43:32 GMT

Hello,

we use a iMX7-Colibri modul.

Currently we have a SRAM mapped in the external EIM-Bus (0x28000000-0x2FFFFFFF) - CS0 area 128MB.

It works well.
Now we like to split the area in 2 regions with CS0 and CS1 with 2 * 64 MB

CS0 (0x28000000-0x2BFFFFFF) CS1 (0x2C000000-0x2FFFFF)
I used CS0 Registers and values as a template, but I had done something wrong.
If I read from CS1 area I got the data form CS0 area. I guess there is a register value not defined.
Please can you assist me, to find the error.

I can see CS0, WR, OE,.. signals, but no CS1 signal.

I read back the register settings and the values are:

IOMUXC_GPR_GPR1: 4f40202d <-- Change to 2 * 64MB

pWEIM->CS0GCR1: 00610089
pWEIM->CS0GCR2: 00001002
pWEIM->CS0WR1: 1f6fffd3

pWEIM->CS1GCR1: 00010089
pWEIM->CS1GCR2: 00001002
pWEIM->CS1WR1: 1f6fffd3

//CS1_B mux port of EIM

pSW_PADEPDC_DATA15 = (DWORD*)Map_OALPAtoVA(IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15, 1);
*pSW_PADEPDC_DATA15 = *pSW_PADEPDC_DATA15 | 0x04; //CS1_B mux port of EIM

Can you help me.

best regards

Re: iMX7 external Bus CS1

igorpadykov — Wed, 22 Aug 2018 06:16:55 GMT

Hi Manfred

according to description IOMUXC_GPR_GPR1 in Reference Manual

ADDRS[10]= 01 - 64 MByte size so for 2 * 64MB settings seems would be:
IOMUXC_GPR_GPR1: 4f40202d ==> 4f40201b

Best regards
igor
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Re: iMX7 external Bus CS1

mahaep — Wed, 22 Aug 2018 06:47:22 GMT

Thank you Igor, now it works fine.