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    <title>i.MX ProcessorsのトピックRe: RGMII : ENET_REF_CLK</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/RGMII-ENET-REF-CLK/m-p/805532#M124349</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Eishi SHIBUSAWA,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;To answer your first question RGMII does require a 125MHz clock externally provided.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;You can find more details regarding this on Table 2-9 of the i.MX6 Hardware Design Guide.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;As for the duty cycle the recommendation is to use good (25-50 ppm) frequency stability and 45%~55% &amp;amp; duty cycle clock source.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I hope this helps!&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 28 Sep 2018 21:18:15 GMT</pubDate>
    <dc:creator>gusarambula</dc:creator>
    <dc:date>2018-09-28T21:18:15Z</dc:date>
    <item>
      <title>RGMII : ENET_REF_CLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RGMII-ENET-REF-CLK/m-p/805531#M124348</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN&gt;Dear Sir&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Customers use the i.MX6DL ENET with RGMII.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Please tell me about RGMII I/F.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The following explanation is on P146 of IMX6SDLIEC Rev.8.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;ENET_REF_CLK is used as a clock source for MII and RGMII modes only.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;RGMII mode uses either GPIO_16 or RGMII_TX_CTL as a clock source.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;For more information on these clocks, see the device Reference Manual and the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG).&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I confirmed the Table 23-1. ENET External Signals (P1062) of IMX6SDLRM Rev.4.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;ENET_REF_CLK : In RMII mode, this signal is the reference clock for receive, transmit, and the control interface.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;(It seems that the ENET_REF_CLK is used only when the MII setting.)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Q1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Does it need the 125MHz clock to ENET_REF_CLK when it is configured the ENET as RGMII?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Q2.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;How is the AC spec (Duty) if it needs the 125MHz clock to the ENET_REF_CLK?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Eishi SHIBUSAWA&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 28 Sep 2018 08:28:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RGMII-ENET-REF-CLK/m-p/805531#M124348</guid>
      <dc:creator>eishishibusawa</dc:creator>
      <dc:date>2018-09-28T08:28:21Z</dc:date>
    </item>
    <item>
      <title>Re: RGMII : ENET_REF_CLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RGMII-ENET-REF-CLK/m-p/805532#M124349</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Eishi SHIBUSAWA,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;To answer your first question RGMII does require a 125MHz clock externally provided.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;You can find more details regarding this on Table 2-9 of the i.MX6 Hardware Design Guide.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;As for the duty cycle the recommendation is to use good (25-50 ppm) frequency stability and 45%~55% &amp;amp; duty cycle clock source.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I hope this helps!&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 28 Sep 2018 21:18:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RGMII-ENET-REF-CLK/m-p/805532#M124349</guid>
      <dc:creator>gusarambula</dc:creator>
      <dc:date>2018-09-28T21:18:15Z</dc:date>
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