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    <title>topic Re: DCD TABLE EXPLANATION in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/DCD-TABLE-EXPLANATION/m-p/804296#M124221</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello C.Himabindu,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Are you referring to the register setup that can be generated by the i.MX6SL LPDDR2 Register Programming Aid?&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/docs/DOC-105968"&gt;https://community.nxp.com/docs/DOC-105968&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In that case the best source of information is the Reference Manual, albeit it’s a bit cumbersome and there are several settings to take care, which is why the programming aid is a very useful tool.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope this helps!&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 29 Aug 2018 16:43:15 GMT</pubDate>
    <dc:creator>gusarambula</dc:creator>
    <dc:date>2018-08-29T16:43:15Z</dc:date>
    <item>
      <title>DCD TABLE EXPLANATION</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DCD-TABLE-EXPLANATION/m-p/804295#M124220</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Please explain the DCD Table in U-Boot for LPDDR2 IMX6SL EVK Board.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&amp;nbsp; &amp;amp; Regards,&lt;/P&gt;&lt;P&gt;C.Himabindu.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 20 Aug 2018 11:06:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DCD-TABLE-EXPLANATION/m-p/804295#M124220</guid>
      <dc:creator>himabindu</dc:creator>
      <dc:date>2018-08-20T11:06:15Z</dc:date>
    </item>
    <item>
      <title>Re: DCD TABLE EXPLANATION</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DCD-TABLE-EXPLANATION/m-p/804296#M124221</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello C.Himabindu,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Are you referring to the register setup that can be generated by the i.MX6SL LPDDR2 Register Programming Aid?&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/docs/DOC-105968"&gt;https://community.nxp.com/docs/DOC-105968&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In that case the best source of information is the Reference Manual, albeit it’s a bit cumbersome and there are several settings to take care, which is why the programming aid is a very useful tool.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope this helps!&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Aug 2018 16:43:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DCD-TABLE-EXPLANATION/m-p/804296#M124221</guid>
      <dc:creator>gusarambula</dc:creator>
      <dc:date>2018-08-29T16:43:15Z</dc:date>
    </item>
    <item>
      <title>Re: DCD TABLE EXPLANATION</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DCD-TABLE-EXPLANATION/m-p/804297#M124222</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thankyou for the above summary.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;C.Himabindu.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 31 Aug 2018 04:30:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DCD-TABLE-EXPLANATION/m-p/804297#M124222</guid>
      <dc:creator>himabindu</dc:creator>
      <dc:date>2018-08-31T04:30:37Z</dc:date>
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