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    <title>topic Re: How to set 2D GPU, 3D GPU clocks to 396MHz frequency ? in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/How-to-set-2D-GPU-3D-GPU-clocks-to-396MHz-frequency/m-p/803554#M124123</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Peter&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;it may be changed by busfreq driver described in&lt;/P&gt;&lt;P&gt;Chapter 24 Dynamic Bus Frequency Driver attached Linux Manual.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 21 Aug 2018 05:20:58 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2018-08-21T05:20:58Z</dc:date>
    <item>
      <title>How to set 2D GPU, 3D GPU clocks to 396MHz frequency ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-set-2D-GPU-3D-GPU-clocks-to-396MHz-frequency/m-p/803551#M124120</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; padding: 0px;"&gt;Dear All,&lt;/P&gt;&lt;DIV style="color: #222222; background-color: #ffffff; border: 0px; font-size: 12.8px; padding: 0px;"&gt; &lt;/DIV&gt;&lt;DIV style="color: #222222; background-color: #ffffff; border: 0px; font-size: 12.8px; padding: 0px;"&gt;&lt;STRONG&gt;i.MAX6Q&amp;nbsp;and 800MHz Memory based custom hardware.&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV style="color: #222222; background-color: #ffffff; border: 0px; font-size: 12.8px; padding: 0px;"&gt; &lt;/DIV&gt;&lt;DIV style="color: #222222; background-color: #ffffff; border: 0px; font-size: 12.8px; padding: 0px;"&gt;The&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 12.8px; padding: 0px;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit; font-size: 12.8px; padding: 0px;"&gt;CCM_CBCMR&lt;/SPAN&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 12.8px; padding: 0px;"&gt;&amp;nbsp;&lt;/SPAN&gt;register controls the clock source for the MMDC (memory controller) interfaces. The i.MX6 ROM configures this register so that the MMDC_CH0_CLK_ROOT and MMDC_CH1_CLK_ROOT clocks are sourced from the PLL2 main output (528 MHz). We can change these clocks to the PLL2-PFD2 output which runs at 396 MHz by adding the following lines into your DCD file in U-boot.&lt;/DIV&gt;&lt;BLOCKQUOTE class="jive-quote" style="color: #222222; border: none; font-size: 12.8px; margin: 0px 0px 0px 40px; padding: 10px 20px;"&gt;&lt;DIV style="border: 0px; font-weight: inherit; font-size: 12.8px; padding: 0px;"&gt;&lt;DIV style="border: 0px; font-weight: inherit; font-size: 12.8px; padding: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 12.8px; padding: 0px;"&gt;/* Configure MMDC clocks for 396 MHz operation */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV style="border: 0px; font-weight: inherit; font-size: 12.8px; padding: 0px;"&gt;&lt;DIV style="border: 0px; font-weight: inherit; font-size: 12.8px; padding: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 12.8px; padding: 0px;"&gt;DATA 4 0x020C4018&amp;nbsp;0x00260324&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But when I get the clock dump I can see following (Please refer following clock dump)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;gpu2d_core - 480000000&lt;/P&gt;&lt;P&gt;gpu2d_core_podf - 480000000&lt;/P&gt;&lt;P&gt;gpu2d_core_sel - 480000000&lt;/P&gt;&lt;P&gt;gpu2d_axi - 198000000&lt;/P&gt;&lt;P&gt;gpu3d_axi - 198000000&lt;/P&gt;&lt;P&gt;pcie_axi_sel - 198000000&lt;/P&gt;&lt;P&gt;vpu_axi_sel - 198000000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;1) If the memory is running 396MHz don't we need to set above clock to 396MHz as well. (I need to use GPU,VPU with high load)&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;2) If I need to set above clocks to 396MHz how I can do it ? Do I need to do this in uboot in the same way I configure MMDC clock ?&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have attached clock dump here with.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Peter.&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;root@remotecockpit:~# cat /sys/kernel/debug/clk/clk_summary | grep mmdc&lt;BR /&gt; mmdc_ch1_axi 0 0 396000000 0 0&lt;BR /&gt; mmdc_ch0_axi 3 3 396000000 0 0&lt;BR /&gt;root@remotecockpit:~# cat /sys/kernel/debug/clk/clk_summary&lt;BR /&gt; clock enable_cnt prepare_cnt rate accuracy phase&lt;BR /&gt;----------------------------------------------------------------------------------------&lt;BR /&gt; anaclk2 0 0 0 0 0&lt;BR /&gt; lvds2_in 0 0 0 0 0&lt;BR /&gt; anaclk1 0 0 0 0 0&lt;BR /&gt; lvds1_in 0 0 0 0 0&lt;BR /&gt; dummy 3 4 0 0 0&lt;BR /&gt; lvds2_sel 0 0 0 0 0&lt;BR /&gt; lvds2_gate 0 0 0 0 0&lt;BR /&gt; usbphy2_gate 1 1 0 0 0&lt;BR /&gt; usbphy1_gate 1 1 0 0 0&lt;BR /&gt; clk24m 0 0 24000000 0 0&lt;BR /&gt; osc 6 6 24000000 0 0&lt;BR /&gt; cko2_sel 0 0 24000000 0 0&lt;BR /&gt; cko2_podf 0 0 24000000 0 0&lt;BR /&gt; cko2 0 0 24000000 0 0&lt;BR /&gt; cko 0 0 24000000 0 0&lt;BR /&gt; gpt_3m 1 1 3000000 0 0&lt;BR /&gt; pll7_bypass_src 1 1 24000000 0 0&lt;BR /&gt; pll7 1 1 480000000 0 0&lt;BR /&gt; pll7_bypass 1 1 480000000 0 0&lt;BR /&gt; pll7_usb_host 1 1 480000000 0 0&lt;BR /&gt; usbphy2 1 1 480000000 0 0&lt;BR /&gt; pll6_bypass_src 1 1 24000000 0 0&lt;BR /&gt; pll6 1 1 500000000 0 0&lt;BR /&gt; pll6_bypass 1 1 500000000 0 0&lt;BR /&gt; pll6_enet 2 2 500000000 0 0&lt;BR /&gt; enet_ref 0 0 125000000 0 0&lt;BR /&gt; pcie_ref 1 1 125000000 0 0&lt;BR /&gt; pcie_ref_125m 1 1 125000000 0 0&lt;BR /&gt; sata_ref 1 1 100000000 0 0&lt;BR /&gt; sata_ref_100m 1 1 100000000 0 0&lt;BR /&gt; lvds1_sel 1 1 100000000 0 0&lt;BR /&gt; lvds1_gate 1 1 100000000 0 0&lt;BR /&gt; pll5_bypass_src 1 1 24000000 0 0&lt;BR /&gt; pll5 1 1 1188000000 0 0&lt;BR /&gt; pll5_bypass 1 1 1188000000 0 0&lt;BR /&gt; pll5_video 1 1 1188000000 0 0&lt;BR /&gt; pll5_post_div 1 1 297000000 0 0&lt;BR /&gt; pll5_video_div 1 1 74250000 0 0&lt;BR /&gt; ipu2_di1_pre_sel 0 0 74250000 0 0&lt;BR /&gt; ipu2_di1_pre 0 0 24750000 0 0&lt;BR /&gt; ipu2_di1_sel 0 0 24750000 0 0&lt;BR /&gt; ipu2_di1 0 0 24750000 0 0&lt;BR /&gt; ipu2_di0_pre_sel 1 1 74250000 0 0&lt;BR /&gt; ipu2_di0_pre 1 1 74250000 0 0&lt;BR /&gt; ipu2_di0_sel 1 1 74250000 0 0&lt;BR /&gt; ipu2_di0 1 1 74250000 0 0&lt;BR /&gt; ipu2_pclk0_sel 1 1 74250000 0 0&lt;BR /&gt; ipu2_pclk0_div 1 1 74250000 0 0&lt;BR /&gt; ipu2_pclk0 1 1 74250000 0 0&lt;BR /&gt; ipu1_di1_pre_sel 0 0 74250000 0 0&lt;BR /&gt; ipu1_di1_pre 0 0 24750000 0 0&lt;BR /&gt; ipu1_di1_sel 0 0 24750000 0 0&lt;BR /&gt; ipu1_di1 0 0 24750000 0 0&lt;BR /&gt; ldb_di1_sel 0 0 74250000 0 0&lt;BR /&gt; ldb_di1_div_7 0 0 10607142 0 0&lt;BR /&gt; ldb_di1_div_sel 0 0 10607142 0 0&lt;BR /&gt; ldb_di1 0 0 10607142 0 0&lt;BR /&gt; ldb_di1_div_3_5 0 0 21214285 0 0&lt;BR /&gt; ldb_di0_sel 0 0 74250000 0 0&lt;BR /&gt; ldb_di0_div_7 0 0 10607142 0 0&lt;BR /&gt; ldb_di0_div_sel 0 0 10607142 0 0&lt;BR /&gt; ldb_di0 0 0 10607142 0 0&lt;BR /&gt; ldb_di0_div_3_5 0 0 21214285 0 0&lt;BR /&gt; pll4_bypass_src 0 0 24000000 0 0&lt;BR /&gt; pll4 0 0 147456000 0 0&lt;BR /&gt; pll4_bypass 0 0 147456000 0 0&lt;BR /&gt; pll4_audio 0 0 147456000 0 0&lt;BR /&gt; pll4_post_div 0 0 36864000 0 0&lt;BR /&gt; pll4_audio_div 0 0 36864000 0 0&lt;BR /&gt; pll3_bypass_src 1 1 24000000 0 0&lt;BR /&gt; pll3 1 1 480000000 0 0&lt;BR /&gt; pll3_bypass 1 1 480000000 0 0&lt;BR /&gt; pll3_usb_otg 3 3 480000000 0 0&lt;BR /&gt; gpu2d_core_sel 0 0 480000000 0 0&lt;BR /&gt; gpu2d_core_podf 0 0 480000000 0 0&lt;BR /&gt; gpu2d_core 0 0 480000000 0 0&lt;BR /&gt; asrc_sel 0 0 480000000 0 0&lt;BR /&gt; asrc_pred 0 0 240000000 0 0&lt;BR /&gt; asrc_podf 0 0 30000000 0 0&lt;BR /&gt; asrc 0 0 30000000 0 0&lt;BR /&gt; esai_sel 0 0 480000000 0 0&lt;BR /&gt; esai_pred 0 0 240000000 0 0&lt;BR /&gt; esai_podf 0 0 30000000 0 0&lt;BR /&gt; esai_extal 0 0 30000000 0 0&lt;BR /&gt; periph2_clk2_sel 0 0 480000000 0 0&lt;BR /&gt; periph2_clk2 0 0 480000000 0 0&lt;BR /&gt; periph_clk2_sel 0 0 480000000 0 0&lt;BR /&gt; periph_clk2 0 0 480000000 0 0&lt;BR /&gt; pll3_60m 0 0 60000000 0 0&lt;BR /&gt; can_root 0 0 30000000 0 0&lt;BR /&gt; can2_serial 0 0 30000000 0 0&lt;BR /&gt; can1_serial 0 0 30000000 0 0&lt;BR /&gt; ecspi_root 0 0 60000000 0 0&lt;BR /&gt; ecspi5 0 0 60000000 0 0&lt;BR /&gt; ecspi4 0 0 60000000 0 0&lt;BR /&gt; ecspi3 0 0 60000000 0 0&lt;BR /&gt; ecspi2 0 0 60000000 0 0&lt;BR /&gt; ecspi1 0 0 60000000 0 0&lt;BR /&gt; pll3_80m 1 1 80000000 0 0&lt;BR /&gt; uart_serial_podf 1 1 80000000 0 0&lt;BR /&gt; uart_serial 1 2 80000000 0 0&lt;BR /&gt; pll3_120m 0 0 120000000 0 0&lt;BR /&gt; pll3_pfd3_454m 0 0 454736842 0 0&lt;BR /&gt; spdif_sel 0 0 454736842 0 0&lt;BR /&gt; spdif_pred 0 0 227368421 0 0&lt;BR /&gt; spdif_podf 0 0 28421053 0 0&lt;BR /&gt; spdif 0 0 28421053 0 0&lt;BR /&gt; pll3_pfd2_508m 0 0 508235294 0 0&lt;BR /&gt; ssi3_sel 0 0 508235294 0 0&lt;BR /&gt; ssi3_pred 0 0 127058824 0 0&lt;BR /&gt; ssi3_podf 0 0 63529412 0 0&lt;BR /&gt; ssi3 0 0 63529412 0 0&lt;BR /&gt; ssi2_sel 0 0 508235294 0 0&lt;BR /&gt; ssi2_pred 0 0 127058824 0 0&lt;BR /&gt; ssi2_podf 0 0 63529412 0 0&lt;BR /&gt; ssi2 0 0 63529412 0 0&lt;BR /&gt; ssi1_sel 0 0 508235294 0 0&lt;BR /&gt; ssi1_pred 0 0 127058824 0 0&lt;BR /&gt; ssi1_podf 0 0 63529412 0 0&lt;BR /&gt; ssi1 0 0 63529412 0 0&lt;BR /&gt; pll3_pfd1_540m 2 2 540000000 0 0&lt;BR /&gt; ipu1_di0_pre_sel 1 1 540000000 0 0&lt;BR /&gt; ipu1_di0_pre 1 1 108000000 0 0&lt;BR /&gt; ipu1_di0_sel 1 1 108000000 0 0&lt;BR /&gt; ipu1_di0 1 1 108000000 0 0&lt;BR /&gt; ipu1_pclk0_sel 1 1 108000000 0 0&lt;BR /&gt; ipu1_pclk0_div 1 1 27000000 0 0&lt;BR /&gt; ipu1_pclk0 1 1 27000000 0 0&lt;BR /&gt; hdmi_isfr 1 1 540000000 0 0&lt;BR /&gt; video_27m 0 0 27000000 0 0&lt;BR /&gt; pll3_pfd0_720m 0 0 720000000 0 0&lt;BR /&gt; usbphy1 0 0 480000000 0 0&lt;BR /&gt; pll2_bypass_src 1 1 24000000 0 0&lt;BR /&gt; pll2 1 1 528000000 0 0&lt;BR /&gt; pll2_bypass 1 1 528000000 0 0&lt;BR /&gt; pll2_bus 1 1 528000000 0 0&lt;BR /&gt; pll2_pfd2_396m 3 3 396000000 0 0&lt;BR /&gt; enfc_sel 0 0 396000000 0 0&lt;BR /&gt; enfc_pred 0 0 79200000 0 0&lt;BR /&gt; enfc_podf 0 0 19800000 0 0&lt;BR /&gt; enfc 0 0 19800000 0 0&lt;BR /&gt; gpmi_io 0 0 19800000 0 0&lt;BR /&gt; emi_sel 0 0 396000000 0 0&lt;BR /&gt; emi_podf 0 0 198000000 0 0&lt;BR /&gt; usdhc4_sel 0 0 396000000 0 0&lt;BR /&gt; usdhc4_podf 0 0 198000000 0 0&lt;BR /&gt; usdhc4 0 0 198000000 0 0&lt;BR /&gt; gpmi_bch 0 0 198000000 0 0&lt;BR /&gt; usdhc3_sel 0 0 396000000 0 0&lt;BR /&gt; usdhc3_podf 0 0 198000000 0 0&lt;BR /&gt; usdhc3 0 0 198000000 0 0&lt;BR /&gt; apbh_dma 0 0 198000000 0 0&lt;BR /&gt; per1_bch 0 0 198000000 0 0&lt;BR /&gt; gpmi_bch_apb 0 0 198000000 0 0&lt;BR /&gt; gpmi_apb 0 0 198000000 0 0&lt;BR /&gt; usdhc2_sel 0 0 396000000 0 0&lt;BR /&gt; usdhc2_podf 0 0 198000000 0 0&lt;BR /&gt; usdhc2 0 0 198000000 0 0&lt;BR /&gt; usdhc1_sel 0 0 396000000 0 0&lt;BR /&gt; usdhc1_podf 0 0 198000000 0 0&lt;BR /&gt; usdhc1 0 0 198000000 0 0&lt;BR /&gt; hsi_tx_sel 1 1 396000000 0 0&lt;BR /&gt; hsi_tx_podf 1 1 198000000 0 0&lt;BR /&gt; hsi_tx 1 1 198000000 0 0&lt;BR /&gt; axi_alt_sel 0 0 396000000 0 0&lt;BR /&gt; periph2_pre 0 0 396000000 0 0&lt;BR /&gt; periph2 0 0 396000000 0 0&lt;BR /&gt; mmdc_ch1_axi 0 0 396000000 0 0&lt;BR /&gt; periph_pre 1 1 396000000 0 0&lt;BR /&gt; periph 3 3 396000000 0 0&lt;BR /&gt; axi_sel 1 1 396000000 0 0&lt;BR /&gt; axi 3 3 198000000 0 0&lt;BR /&gt; openvg_axi 0 0 198000000 0 0&lt;BR /&gt; mlb 0 0 198000000 0 0&lt;BR /&gt; vpu_axi_sel 0 0 198000000 0 0&lt;BR /&gt; vpu_axi_podf 0 0 198000000 0 0&lt;BR /&gt; vpu_axi 0 0 198000000 0 0&lt;BR /&gt; vdo_axi_sel 0 0 198000000 0 0&lt;BR /&gt; vdo_axi 0 0 198000000 0 0&lt;BR /&gt; vdoa 0 0 198000000 0 0&lt;BR /&gt; emi_slow_sel 1 1 198000000 0 0&lt;BR /&gt; emi_slow_podf 1 1 99000000 0 0&lt;BR /&gt; eim_slow 1 1 99000000 0 0&lt;BR /&gt; pcie_axi_sel 1 1 198000000 0 0&lt;BR /&gt; pcie_axi 1 1 198000000 0 0&lt;BR /&gt; gpu3d_axi 0 0 198000000 0 0&lt;BR /&gt; gpu2d_axi 0 0 198000000 0 0&lt;BR /&gt; mmdc_ch0_axi 3 3 396000000 0 0&lt;BR /&gt; gpu3d_core_sel 0 0 396000000 0 0&lt;BR /&gt; gpu3d_core_podf 0 0 396000000 0 0&lt;BR /&gt; gpu3d_core 0 0 396000000 0 0&lt;BR /&gt; ipu2_sel 1 1 396000000 0 0&lt;BR /&gt; ipu2_podf 1 1 198000000 0 0&lt;BR /&gt; ipu2 1 1 198000000 0 0&lt;BR /&gt; ipu2_pclk1_sel 0 0 198000000 0 0&lt;BR /&gt; ipu2_pclk1_div 0 0 0 0 0&lt;BR /&gt; ipu2_pclk1 0 0 0 0 0&lt;BR /&gt; dcic2 0 0 198000000 0 0&lt;BR /&gt; ipu1_sel 1 1 396000000 0 0&lt;BR /&gt; ipu1_podf 1 1 198000000 0 0&lt;BR /&gt; ipu1 1 1 198000000 0 0&lt;BR /&gt; ipu1_pclk1_sel 0 0 198000000 0 0&lt;BR /&gt; ipu1_pclk1_div 0 0 0 0 0&lt;BR /&gt; ipu1_pclk1 0 0 0 0 0&lt;BR /&gt; dcic1 0 0 198000000 0 0&lt;BR /&gt; ahb 7 7 99000000 0 0&lt;BR /&gt; sdma 8 2 99000000 0 0&lt;BR /&gt; sata 0 0 99000000 0 0&lt;BR /&gt; rom 1 1 99000000 0 0&lt;BR /&gt; ocram 2 2 99000000 0 0&lt;BR /&gt; hdmi_iahb 1 1 99000000 0 0&lt;BR /&gt; esai_mem 0 0 99000000 0 0&lt;BR /&gt; esai_ipg 0 0 99000000 0 0&lt;BR /&gt; caam_aclk 1 1 99000000 0 0&lt;BR /&gt; caam_mem 1 1 99000000 0 0&lt;BR /&gt; asrc_mem 0 0 99000000 0 0&lt;BR /&gt; asrc_ipg 0 0 99000000 0 0&lt;BR /&gt; cko1_sel 0 0 99000000 0 0&lt;BR /&gt; cko1_podf 0 0 12375000 0 0&lt;BR /&gt; cko1 0 0 12375000 0 0&lt;BR /&gt; ipg 3 4 49500000 0 0&lt;BR /&gt; usboh3 0 0 49500000 0 0&lt;BR /&gt; uart_ipg 1 2 49500000 0 0&lt;BR /&gt; ssi3_ipg 0 0 49500000 0 0&lt;BR /&gt; ssi2_ipg 0 0 49500000 0 0&lt;BR /&gt; ssi1_ipg 0 1 49500000 0 0&lt;BR /&gt; spdif_gclk 0 0 49500000 0 0&lt;BR /&gt; spba 0 0 49500000 0 0&lt;BR /&gt; iim 0 0 49500000 0 0&lt;BR /&gt; gpt_ipg 1 1 49500000 0 0&lt;BR /&gt; enet 0 0 49500000 0 0&lt;BR /&gt; can2_ipg 0 0 49500000 0 0&lt;BR /&gt; can1_ipg 0 0 49500000 0 0&lt;BR /&gt; caam_ipg 1 1 49500000 0 0&lt;BR /&gt; ipg_per 0 0 49500000 0 0&lt;BR /&gt; pwm4 0 0 49500000 0 0&lt;BR /&gt; pwm3 0 0 49500000 0 0&lt;BR /&gt; pwm2 0 0 49500000 0 0&lt;BR /&gt; pwm1 0 0 49500000 0 0&lt;BR /&gt; i2c3 0 0 49500000 0 0&lt;BR /&gt; i2c2 0 0 49500000 0 0&lt;BR /&gt; i2c1 0 0 49500000 0 0&lt;BR /&gt; gpt_ipg_per 0 0 49500000 0 0&lt;BR /&gt; step 1 1 396000000 0 0&lt;BR /&gt; pll1_sw 1 1 396000000 0 0&lt;BR /&gt; arm 2 2 396000000 0 0&lt;BR /&gt; twd 1 1 198000000 0 0&lt;BR /&gt; pll2_198m 0 0 198000000 0 0&lt;BR /&gt; pll2_pfd1_594m 0 0 594000000 0 0&lt;BR /&gt; gpu3d_shader_sel 0 0 594000000 0 0&lt;BR /&gt; gpu3d_shader 0 0 594000000 0 0&lt;BR /&gt; pll2_pfd0_352m 0 0 352000000 0 0&lt;BR /&gt; pll1_bypass_src 0 0 24000000 0 0&lt;BR /&gt; pll1_bypass 0 0 24000000 0 0&lt;BR /&gt; pll1_sys 0 0 24000000 0 0&lt;BR /&gt; pll1 0 0 996000000 0 0&lt;BR /&gt; ckih1 0 0 0 0 0&lt;BR /&gt; ckil 0 0 32768 0 0&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 20 Aug 2018 16:50:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-set-2D-GPU-3D-GPU-clocks-to-396MHz-frequency/m-p/803551#M124120</guid>
      <dc:creator>peteramond</dc:creator>
      <dc:date>2018-08-20T16:50:20Z</dc:date>
    </item>
    <item>
      <title>Re: How to set 2D GPU, 3D GPU clocks to 396MHz frequency ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-set-2D-GPU-3D-GPU-clocks-to-396MHz-frequency/m-p/803552#M124121</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Peter&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;one can look at i.MX6SDL software (memory is running 400MHz), use&lt;/P&gt;&lt;P&gt;"imx6solosabresd" configuration and sect.5.1 Build configurations attached Yocto&lt;/P&gt;&lt;P&gt;Guide. In general, if the memory is running 396MHz there is no need to set GPU,VPU&amp;nbsp;&lt;/P&gt;&lt;P&gt;clock to 396MHz.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Aug 2018 02:22:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-set-2D-GPU-3D-GPU-clocks-to-396MHz-frequency/m-p/803552#M124121</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-08-21T02:22:22Z</dc:date>
    </item>
    <item>
      <title>Re: How to set 2D GPU, 3D GPU clocks to 396MHz frequency ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-set-2D-GPU-3D-GPU-clocks-to-396MHz-frequency/m-p/803553#M124122</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&amp;nbsp;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/igorpadykov"&gt;igorpadykov&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Why it show following as 198MHz in above clock dump ?&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;gpu2d_axi - 198000000&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;gpu3d_axi - 198000000&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;pcie_axi_sel - 198000000&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;vpu_axi_sel - 198000000&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;STRONG&gt;Shouldn't it be 396MHz ?&lt;/STRONG&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Regards,&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Peter&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Aug 2018 05:00:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-set-2D-GPU-3D-GPU-clocks-to-396MHz-frequency/m-p/803553#M124122</guid>
      <dc:creator>peteramond</dc:creator>
      <dc:date>2018-08-21T05:00:10Z</dc:date>
    </item>
    <item>
      <title>Re: How to set 2D GPU, 3D GPU clocks to 396MHz frequency ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-set-2D-GPU-3D-GPU-clocks-to-396MHz-frequency/m-p/803554#M124123</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Peter&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;it may be changed by busfreq driver described in&lt;/P&gt;&lt;P&gt;Chapter 24 Dynamic Bus Frequency Driver attached Linux Manual.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Aug 2018 05:20:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-set-2D-GPU-3D-GPU-clocks-to-396MHz-frequency/m-p/803554#M124123</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-08-21T05:20:58Z</dc:date>
    </item>
    <item>
      <title>Re: How to set 2D GPU, 3D GPU clocks to 396MHz frequency ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-set-2D-GPU-3D-GPU-clocks-to-396MHz-frequency/m-p/803555#M124124</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&amp;nbsp;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/igorpadykov"&gt;igorpadykov&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can't we lover DDR frequency than 396MHz?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Normally I add following line to uboot to run DDR in 396MHz. Can't we lover this frequency in uboot ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;DIV style="color: #222222; border: 0px; font-weight: inherit; font-size: 12.8px;"&gt;&lt;DIV style="border: 0px; font-weight: inherit; font-size: 12.8px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 12.8px;"&gt;* Configure MMDC clocks for 396 MHz operation */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV style="color: #222222; border: 0px; font-weight: inherit; font-size: 12.8px;"&gt;&lt;DIV style="border: 0px; font-weight: inherit; font-size: 12.8px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 12.8px;"&gt;DATA 4 0x020C4018&amp;nbsp;0x00260324&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Peter.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Aug 2018 09:33:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-set-2D-GPU-3D-GPU-clocks-to-396MHz-frequency/m-p/803555#M124124</guid>
      <dc:creator>peteramond</dc:creator>
      <dc:date>2018-08-21T09:33:02Z</dc:date>
    </item>
    <item>
      <title>Re: How to set 2D GPU, 3D GPU clocks to 396MHz frequency ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-set-2D-GPU-3D-GPU-clocks-to-396MHz-frequency/m-p/803556#M124125</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Peter&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;you can do that in similar manner as linux busfreq driver:&lt;/P&gt;&lt;P&gt;jump to iram, reconfigure ddr frequency, then jump to ddr again.&lt;/P&gt;&lt;P&gt;Seems you should write custom codes for that procedure.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Aug 2018 10:16:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-set-2D-GPU-3D-GPU-clocks-to-396MHz-frequency/m-p/803556#M124125</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-08-21T10:16:37Z</dc:date>
    </item>
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